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    Searched defs:RW (Results 1 - 6 of 6) sorted by null

  /external/compiler-rt/lib/tsan/tests/rtl/
tsan_test_util.h 36 RW,
  /external/llvm/utils/TableGen/
CodeGenSchedule.cpp 188 // Visit each RW in the sequence selected by the current variant.
295 CodeGenSchedRW &RW = getSchedRW(MatchDef);
296 if (RW.IsAlias)
298 RW.Aliases.push_back(*AI);
431 " Ensure only one SchedAlias exists per RW.");
463 // Index zero reserved for invalid RW.
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  /external/clang/test/Layout/
ms-x86-alias-avoidance-padding.cpp 304 struct RW { char c; };
313 struct RX7 : virtual RW { RA a; };
314 struct RX8 : RA, virtual RW {};
485 // CHECK-NEXT: 8 | struct RW (virtual base)
497 // CHECK-X64-NEXT: 16 | struct RW (virtual base)
510 // CHECK-NEXT: 4 | struct RW (virtual base)
521 // CHECK-X64-NEXT: 8 | struct RW (virtual base)
  /toolchain/binutils/binutils-2.25/opcodes/
rl78-decode.c 63 #define RW(x) ((x)+RL78_Reg_AX)
111 #define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
122 #define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
217 int rw AU = (op[0] >> 1) & 0x03;
223 printf (" rw = 0x%x\n", rw);
227 ID(add); W(); DR(AX); SRW(rw); Fzac;
623 int rw AU = (op[0] >> 1) & 0x03;
629 printf (" rw = 0x%x\n", rw);
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  /external/llvm/lib/Target/Hexagon/
HexagonBitTracker.cpp 84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
89 return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
90 : BT::BitMask(RW, 2*RW-1);
203 // Extract RW low bits of the cell.
204 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
206 assert(RW <= RC.width());
207 return eXTR(RC, 0, RW);
209 // Extract RW high bits of the cell.
210 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
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  /external/clang/lib/CodeGen/
CGBuiltin.cpp 663 Value *Locality, *RW, *Address = EmitScalarExpr(E->getArg(0));
665 RW = (E->getNumArgs() > 1) ? EmitScalarExpr(E->getArg(1)) :
671 return RValue::get(Builder.CreateCall(F, {Address, RW, Locality, Data}));
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