/external/llvm/lib/Target/NVPTX/ |
NVPTXRegisterInfo.h | 52 const char *getName(unsigned RegNo) const { 54 O << "reg" << RegNo;
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NVPTXAsmPrinter.cpp | 499 unsigned RegNo = MI->getOperand(0).getReg(); 500 if (TargetRegisterInfo::isVirtualRegister(RegNo)) { 502 getVirtualRegisterName(RegNo)); 505 nvptxSubtarget->getRegisterInfo()->getName(RegNo)); [all...] |
/art/compiler/utils/arm64/ |
managed_register_arm64.cc | 45 return (IsGPRegister() == other.IsGPRegister()) && (RegNo() == other.RegNo()); 48 int Arm64ManagedRegister::RegNo() const { 67 int low = RegNo(); 79 int high = RegNo();
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/external/llvm/lib/Target/WebAssembly/InstPrinter/ |
WebAssemblyInstPrinter.cpp | 39 unsigned RegNo) const { 40 assert(RegNo != WebAssemblyFunctionInfo::UnusedReg); 42 OS << "$" << RegNo;
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
PPCInstPrinter.cpp | 39 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 40 const char *RegName = getRegisterName(RegNo); 355 unsigned RegNo; 358 case PPC::CR0: RegNo = 0; break; 359 case PPC::CR1: RegNo = 1; break; 360 case PPC::CR2: RegNo = 2; break; 361 case PPC::CR3: RegNo = 3; break; 362 case PPC::CR4: RegNo = 4; break; 363 case PPC::CR5: RegNo = 5; break; 364 case PPC::CR6: RegNo = 6; break [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyAsmPrinter.cpp | 81 MVT getRegType(unsigned RegNo) const; 92 MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const { 94 TargetRegisterInfo::isVirtualRegister(RegNo) ? 95 MRI->getRegClass(RegNo) : 96 MRI->getTargetRegisterInfo()->getMinimalPhysRegClass(RegNo); 100 DEBUG(errs() << "Unknown type for register number: " << RegNo); 106 unsigned RegNo = MO.getReg(); 107 assert(TargetRegisterInfo::isVirtualRegister(RegNo) && 109 assert(!MFI->isVRegStackified(RegNo)); 110 unsigned WAReg = MFI->getWAReg(RegNo); [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineOperand.h | 145 unsigned RegNo; // For MO_Register. 165 // Register number is in SmallContents.RegNo. 269 return SmallContents.RegNo; 616 Op.SmallContents.RegNo = Reg;
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 534 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); 539 return RegNo; 544 return 2 * RegNo; [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86Operand.h | 45 unsigned RegNo; 99 return Reg.RegNo; 389 static unsigned getGR32FromGR64(unsigned RegNo) { 390 switch (RegNo) { 414 unsigned RegNo = getReg(); 415 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo)) 416 RegNo = getGR32FromGR64(RegNo); 417 Inst.addOperand(MCOperand::createReg(RegNo)); 475 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc [all...] |
X86AsmParser.cpp | 749 bool OmitRegisterFromClobberLists(unsigned RegNo) override; 815 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 817 void SetFrameRegister(unsigned RegNo) override; 892 bool X86AsmParser::ParseRegister(unsigned &RegNo, 895 RegNo = 0; 913 RegNo = MatchRegisterName(Tok.getString()); 916 if (RegNo == 0) 917 RegNo = MatchRegisterName(Tok.getString().lower()); 921 if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS) 922 RegNo = 0 [all...] |
/external/llvm/utils/TableGen/ |
RegisterInfoEmitter.cpp | 418 int RegNo = I->second[i]; 419 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 422 OS << " { " << getQualifiedName(I->first) << ", " << RegNo [all...] |
/external/llvm/lib/Target/Sparc/AsmParser/ |
SparcAsmParser.cpp | 53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 76 // returns true if Tok is matched to a register and returns register in RegNo. 77 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, 559 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) 564 RegNo = 0; 569 if (matchRegisterName(Tok, RegNo, regKind)) { 737 unsigned RegNo, RegKind; 738 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) 743 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); 796 unsigned RegNo; [all...] |
/external/llvm/lib/Target/X86/ |
X86FloatingPoint.cpp | 171 unsigned getSlot(unsigned RegNo) const { 172 assert(RegNo < NumFPRegs && "Regno out of range!"); 173 return RegMap[RegNo]; 176 /// isLive - Is RegNo currently live in the stack? 177 bool isLive(unsigned RegNo) const { 178 unsigned Slot = getSlot(RegNo); 179 return Slot < StackTop && Stack[Slot] == RegNo; 190 /// FP<RegNo> register. 191 unsigned getSTReg(unsigned RegNo) const [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
AsmPrinter.cpp | 663 unsigned RegNo = MI->getOperand(0).getReg(); 668 << PrintReg(RegNo, MF->getSubtarget().getRegisterInfo()); [all...] |
/external/llvm/lib/Target/AMDGPU/AsmParser/ |
AMDGPUAsmParser.cpp | 85 unsigned RegNo; 197 return Reg.RegNo; 300 static std::unique_ptr<AMDGPUOperand> CreateReg(unsigned RegNo, SMLoc S, 306 Op->Reg.RegNo = RegNo; 369 bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const; 415 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 519 bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 526 RegNo = getRegForName(RegName); 528 if (RegNo) { [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonFrameLowering.cpp | 200 unsigned RegNo = 0; 203 if (*SubRegs > RegNo) 204 RegNo = *SubRegs; 206 if (!RegNo || *SubRegs < RegNo) 207 RegNo = *SubRegs; 210 return RegNo; [all...] |
/external/llvm/lib/Target/PowerPC/AsmParser/ |
PPCAsmParser.cpp | 257 unsigned &RegNo, int64_t &IntVal); 259 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 320 unsigned RegNo = TRI->getEncodingValue(I->first); 321 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 322 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 336 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 337 UsedRegMask &= ~(1 << (31-RegNo)); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/lib/MC/MCParser/ |
AsmParser.cpp | [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | 139 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 318 unsigned getReg(int RC, int RegNo); 320 unsigned getGPR(int RegNo); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | 370 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; [all...] |