/external/clang/lib/StaticAnalyzer/Core/ |
SimpleConstraintManager.h | 25 SubEngine *SU; 29 : SU(subengine), SVB(SB) {}
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/external/llvm/lib/CodeGen/ |
DFAPacketizer.cpp | 214 // Generate MI -> SU map. 217 SUnit *SU = &VLIWScheduler->SUnits[i]; 218 MIToSUnit[SU->getInstr()] = SU;
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CriticalAntiDepBreaker.cpp | 127 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up 129 static const SDep *CriticalPathStep(const SUnit *SU) { 133 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end(); 440 const SUnit *SU = &SUnits[i]; 441 MISUnitMap[SU->getInstr()] = SU; 442 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency) 443 Max = SU; [all...] |
ScheduleDAGInstrs.cpp | 207 /// the exit SU to the register defs and use list. This is because we want to 245 /// MO is an operand of SU's instruction that defines a physical register. Add 246 /// data dependencies from SU to any uses of the physical register. 247 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { 248 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 259 SUnit *UseSU = I->SU; 260 if (UseSU == SU) 269 Dep = SDep(SU, SDep::Artificial); 273 SU->hasPhysRegDefs = true; 274 Dep = SDep(SU, SDep::Data, *Alias) [all...] |
MachineScheduler.cpp | 542 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { 559 // SU->TopReadyCycle was set to CurrCycle when it was scheduled. However, 561 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) 562 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); 569 /// releaseSuccessors - Call releaseSucc on each of SU's successors. 570 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { 571 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 573 releaseSucc(SU, &*I); 581 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back(); 83 SU->SchedulingPref = Sched::None; 85 SU->SchedulingPref = TLI.getSchedulingPreference(N); 86 return SU; 90 SUnit *SU = newSUnit(Old->getNode()); 91 SU->OrigNode = Old->OrigNode; 92 SU->Latency = Old->Latency; 93 SU->isVRegCycle = Old->isVRegCycle; 94 SU->isCall = Old->isCall; 95 SU->isCallOp = Old->isCallOp [all...] |
ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { 72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, 110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 145 static unsigned numberCtrlDepsInSU(SUnit *SU) { 147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 155 static unsigned numberCtrlPredInSU(SUnit *SU) { [all...] |
ScheduleDAGRRList.cpp | 185 /// IsReachable - Checks if SU is reachable from TargetSU. 186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { 187 return Topo.IsReachable(SU, TargetSU); 190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { 193 return Topo.WillCreateCycle(SU, TargetSU); 196 /// AddPred - adds a predecessor edge to SUnit SU. 199 void AddPred(SUnit *SU, const SDep &D) { 200 Topo.AddPred(SU, D.getSUnit()); 201 SU->addPred(D) [all...] |
/external/eigen/blas/fortran/ |
srotmg.f | 55 + SQ2,STEMP,SU,TWO,ZERO 86 SU = ONE - SH12*SH21 88 IF (.NOT.SU.LE.ZERO) GO TO 30 93 SD1 = SD1/SU 94 SD2 = SD2/SU 95 SX1 = SX1*SU 106 SU = ONE + SH11*SH22 107 STEMP = SD2/SU 108 SD2 = SD1/SU 110 SX1 = SY1*SU [all...] |
/external/llvm/include/llvm/CodeGen/ |
ScheduleDAGInstrs.h | 36 SUnit *SU; 38 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) 39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} 51 unsigned OperandIndex, SUnit *SU) 52 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} 58 SUnit *SU; 62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) { [all...] |
MachineScheduler.h | 205 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 209 virtual void releaseTopNode(SUnit *SU) = 0; 212 virtual void releaseBottomNode(SUnit *SU) = 0; 290 /// \brief Add a DAG edge to the given SU with the given predecessor 334 void updateQueues(SUnit *SU, bool IsTopNode); 348 void releaseSucc(SUnit *SU, SDep *SuccEdge); 349 void releaseSuccessors(SUnit *SU); 350 void releasePred(SUnit *SU, SDep *PredEdge); 351 void releasePredecessors(SUnit *SU); 367 // Map each SU to its summary of pressure changes. This array is updated fo [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600MachineScheduler.cpp | 58 SUnit *SU = nullptr; 98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || 101 SU = pickAlu(); 102 if (!SU && !PhysicalRegCopy.empty()) { 103 SU = PhysicalRegCopy.front(); 106 if (SU) { 113 if (!SU) { 115 SU = pickOther(IDFetch); 116 if (SU) 121 if (!SU) { [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { 30 if (SUnits[su].getInstr()->isCall()) 31 LastSequentialCall = &(SUnits[su]); 33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall) 34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier)); 38 /// Check if scheduling of this SU is possible 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { 44 if (!SU || !SU->getInstr() [all...] |
HexagonMachineScheduler.h | 87 bool isResourceAvailable(SUnit *SU); 88 bool reserveResources(SUnit *SU); 115 SUnit *SU; 123 SchedCandidate(): SU(nullptr), SCost(0) {} 176 bool checkHazard(SUnit *SU); 178 void releaseNode(SUnit *SU, unsigned ReadyCycle); 182 void bumpNode(SUnit *SU); 186 void removeReady(SUnit *SU); 214 void schedNode(SUnit *SU, bool IsTopNode) override; 216 void releaseTopNode(SUnit *SU) override [all...] |
/frameworks/opt/calendar/src/com/android/calendarcommon2/ |
EventRecurrence.java | 41 public static final int SU = 0x00010000; 55 public int wkst; // SU, MO, TU, etc. 129 sParseWeekdayMap.put("SU", SU); 164 * Converts one of the Calendar.SUNDAY constants to the SU, MO, etc. 173 return SU; 196 return SU; 217 case SU: 237 * Converts one of the SU, MO, etc. constants to the Calendar.SUNDAY 245 case SU [all...] |