| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 32 const R600InstrInfo * TII;
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| SIISelLowering.h | 24 const SIInstrInfo * TII;
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| R600RegisterInfo.h | 28 const TargetInstrInfo &TII;
30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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| SIRegisterInfo.h | 28 const TargetInstrInfo &TII;
30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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| AMDGPUConvertToISA.cpp | 49 const AMDGPUInstrInfo * TII =
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
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| AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII;
36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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| /external/llvm/include/llvm/CodeGen/ |
| MachineSSAUpdater.h | 54 const TargetInstrInfo *TII;
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| /external/llvm/lib/Target/AMDGPU/ |
| R600RegisterInfo.cpp | 31 const R600InstrInfo *TII =
54 TII->reserveIndirectRegisters(Reserved, MF);
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 150 const SystemZInstrInfo *TII = ST->getInstrInfo();
152 if (TII->isRxSBGMask(Imm.getZExtValue(), BitSize, Start, End))
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| SystemZLDCleanup.cpp | 34 : MachineFunctionPass(ID), TII(nullptr), MF(nullptr) {}
48 const SystemZInstrInfo *TII;
67 TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
118 TII->get(TargetOpcode::COPY), SystemZ::R2D)
138 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
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| /external/llvm/lib/Target/XCore/ |
| XCoreFrameToArgsOffsetElim.cpp | 46 const XCoreInstrInfo &TII =
57 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
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| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.h | 37 const TargetInstrInfo *TII;
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| DeadMachineInstructionElim.cpp | 36 const TargetInstrInfo *TII;
99 TII = MF.getSubtarget().getInstrInfo();
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| ProcessImplicitDefs.cpp | 29 const TargetInstrInfo *TII;
90 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
142 TII = MF.getSubtarget().getInstrInfo();
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 32 const TargetInstrInfo *TII;
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| /external/llvm/lib/Target/AArch64/ |
| AArch64CleanupLocalDynamicTLSPass.cpp | 95 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
100 TII->get(TargetOpcode::COPY),
113 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
122 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
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| AArch64ExpandPseudoInsts.cpp | 39 const AArch64InstrInfo *TII;
102 const AArch64InstrInfo *TII, unsigned ChunkIdx) {
110 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
120 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
153 const AArch64InstrInfo *TII) {
177 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
197 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
222 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
287 const AArch64InstrInfo *TII) {
360 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 48 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
54 !(TII.getSubtarget().isLikeA9() && LastMI->mayLoadOrStore()) &&
63 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
64 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
65 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
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| /external/llvm/lib/Target/PowerPC/ |
| PPCEarlyReturn.cpp | 55 const TargetInstrInfo *TII;
86 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
98 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
114 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
177 TII = MF.getSubtarget().getInstrInfo();
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyLowerBrUnless.cpp | 60 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break;
86 case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break
[all...] |
| WebAssemblyRegisterInfo.cpp | 76 const auto *TII = MF.getSubtarget().getInstrInfo();
79 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::CONST_I32), OffsetReg)
81 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::ADD_I32), OffsetReg)
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 33 const TargetInstrInfo &TII;
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.h | 27 const HexagonInstrInfo &tii, MachineFunction &mf);
38 const HexagonInstrInfo &TII;
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| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 57 const MSP430InstrInfo *TII =
72 BlockSize += TII->GetInstSizeInBytes(MBBI);
109 MBBStartOffset += TII->GetInstSizeInBytes(I);
156 TII->ReverseBranchCondition(Cond);
157 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
163 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 109 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
113 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
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