| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 36 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
38 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
45 dbgs() << ' ' << PrintReg(Hints[I], TRI);
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| CriticalAntiDepBreaker.h | 38 const TargetRegisterInfo *TRI;
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| DeadMachineInstructionElim.cpp | 34 const TargetRegisterInfo *TRI;
98 TRI = MF.getSubtarget().getRegisterInfo();
146 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
162 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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| RegAllocBase.h | 61 const TargetRegisterInfo *TRI;
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
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| TargetFrameLoweringImpl.cpp | 63 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
64 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
70 SavedRegs.resize(TRI.getNumRegs());
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| ProcessImplicitDefs.cpp | 30 const TargetRegisterInfo *TRI;
108 !TRI->regsOverlap(Reg, UserReg))
143 TRI = MF.getSubtarget().getRegisterInfo();
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| StackMapLivenessAnalysis.cpp | 52 const TargetRegisterInfo *TRI;
107 TRI = MF.getSubtarget().getRegisterInfo();
124 LiveRegs.init(TRI);
158 uint32_t *Mask = MF.allocateRegisterMask(TRI->getNumRegs());
163 TRI->adjustStackMapLiveOutMask(Mask);
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| AggressiveAntiDepBreaker.h | 47 /// Number of non-virtual target registers (i.e. TRI->getNumRegs()).
116 const TargetRegisterInfo *TRI;
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| ExpandPostRAPseudos.cpp | 33 const TargetRegisterInfo *TRI;
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
186 TRI = MF.getSubtarget().getRegisterInfo();
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| RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI;
60 CoalescerPair(const TargetRegisterInfo &tri)
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
67 const TargetRegisterInfo &tri)
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
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| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.h | 26 const TargetRegisterInfo *TRI;
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| AArch64DeadRegisterDefinitionsPass.cpp | 38 const TargetRegisterInfo *TRI;
68 if (TRI->regsOverlap(Reg, MO.getReg()))
135 TRI = MF.getSubtarget().getRegisterInfo();
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| AArch64StorePairSuppress.cpp | 31 const TargetRegisterInfo *TRI;
120 TRI = ST.getRegisterInfo();
145 if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
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| /external/llvm/include/llvm/CodeGen/ |
| LivePhysRegs.h | 44 const TargetRegisterInfo *TRI;
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {}
54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) {
55 assert(TRI && "Invalid TargetRegisterInfo pointer.");
56 LiveRegs.setUniverse(TRI->getNumRegs());
60 void init(const TargetRegisterInfo *TRI) {
61 assert(TRI && "Invalid TargetRegisterInfo pointer.");
62 this->TRI = TRI
[all...] |
| LiveStackAnalysis.h | 29 const TargetRegisterInfo *TRI;
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| LiveRegMatrix.h | 39 const TargetRegisterInfo *TRI;
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| LiveVariables.h | 132 const TargetRegisterInfo *TRI;
204 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
240 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
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| ResourcePriorityQueue.h | 60 const TargetRegisterInfo *TRI;
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.h | 34 const TargetRegisterInfo &TRI;
38 DwarfExpression(const TargetRegisterInfo &TRI,
40 : TRI(TRI), DwarfVersion(DwarfVersion) {}
111 DebugLocDwarfExpression(const TargetRegisterInfo &TRI,
113 : DwarfExpression(TRI, DwarfVersion), BS(BS) {}
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 33 const TargetRegisterInfo *TRI;
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 98 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
102 TRI->needsStackRealignment(MF);
107 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
109 return MFI->hasVarSizedObjects() && TRI->needsStackRealignment(MF);
114 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
123 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
124 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
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| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 34 const X86RegisterInfo *TRI;
82 const TargetRegisterInfo *TRI,
88 const TargetRegisterInfo *TRI) const override;
93 const TargetRegisterInfo *TRI) const override;
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| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRLiveRanges.cpp | 114 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
134 if (TRI->isSGPRClass(MRI.getRegClass(Def))) {
182 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
188 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
196 << PrintReg(Reg, TRI, 0)
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| SIFrameLowering.cpp | 68 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
78 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue(
83 PreloadedPrivateBufferReg = TRI->getPreloadedValue(
118 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) {
137 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) {
147 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg));
158 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg));
174 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchRsrcReg) &&
175 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchWaveOffsetReg));
177 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1)
[all...] |
| SILowerI1Copies.cpp | 77 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
111 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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