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    Searched defs:VirtReg (Results 1 - 7 of 7) sorted by null

  /external/llvm/include/llvm/CodeGen/
LiveIntervalUnion.h 87 void unify(LiveInterval &VirtReg, const LiveRange &Range);
88 void unify(LiveInterval &VirtReg) {
89 unify(VirtReg, VirtReg);
93 void extract(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg) {
95 extract(VirtReg, VirtReg);
113 LiveInterval *VirtReg;
114 LiveInterval::iterator VirtRegI; // current position in VirtReg
    [all...]
ScheduleDAGInstrs.h 34 unsigned VirtReg;
39 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
42 return TargetRegisterInfo::virtReg2Index(VirtReg);
  /external/llvm/lib/CodeGen/
VirtRegMap.cpp 84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
85 unsigned Hint = MRI->getSimpleHint(VirtReg);
90 return getPhys(VirtReg) == Hint;
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
103 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
104 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
106 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC)
    [all...]
RegAllocFast.cpp 72 unsigned VirtReg; // Virtual register number.
78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
113 // PhysRegState - One of the RegState enums, or a virtreg.
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
172 void killVirtReg(unsigned VirtReg);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const
    [all...]
LiveDebugVariables.cpp 307 /// lookupVirtReg - Find the EC leader for VirtReg or null.
308 UserValue *lookupVirtReg(unsigned VirtReg);
346 void mapVirtReg(unsigned VirtReg, UserValue *EC);
476 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
477 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
478 UserValue *&Leader = virtRegToEqClass[VirtReg];
482 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
483 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
916 unsigned VirtReg = Loc.getReg();
917 if (VRM.isAssignedReg(VirtReg) &
    [all...]
MachineBasicBlock.cpp 391 unsigned VirtReg = I->getOperand(0).getReg();
392 if (!MRI.constrainRegClass(VirtReg, RC))
394 return VirtReg;
398 unsigned VirtReg = MRI.createVirtualRegister(RC);
399 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
403 return VirtReg;
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp     [all...]

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