1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 33 #include "brw_context.h" 34 #include "brw_defines.h" 35 #include "brw_eu.h" 36 37 #include "glsl/ralloc.h" 38 39 /* Returns the corresponding conditional mod for swapping src0 and 40 * src1 in e.g. CMP. 41 */ 42 uint32_t 43 brw_swap_cmod(uint32_t cmod) 44 { 45 switch (cmod) { 46 case BRW_CONDITIONAL_Z: 47 case BRW_CONDITIONAL_NZ: 48 return cmod; 49 case BRW_CONDITIONAL_G: 50 return BRW_CONDITIONAL_L; 51 case BRW_CONDITIONAL_GE: 52 return BRW_CONDITIONAL_LE; 53 case BRW_CONDITIONAL_L: 54 return BRW_CONDITIONAL_G; 55 case BRW_CONDITIONAL_LE: 56 return BRW_CONDITIONAL_GE; 57 default: 58 return ~0; 59 } 60 } 61 62 63 /* How does predicate control work when execution_size != 8? Do I 64 * need to test/set for 0xffff when execution_size is 16? 65 */ 66 void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value ) 67 { 68 p->current->header.predicate_control = BRW_PREDICATE_NONE; 69 70 if (value != 0xff) { 71 if (value != p->flag_value) { 72 brw_push_insn_state(p); 73 brw_MOV(p, brw_flag_reg(), brw_imm_uw(value)); 74 p->flag_value = value; 75 brw_pop_insn_state(p); 76 } 77 78 p->current->header.predicate_control = BRW_PREDICATE_NORMAL; 79 } 80 } 81 82 void brw_set_predicate_control( struct brw_compile *p, GLuint pc ) 83 { 84 p->current->header.predicate_control = pc; 85 } 86 87 void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse) 88 { 89 p->current->header.predicate_inverse = predicate_inverse; 90 } 91 92 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional ) 93 { 94 p->current->header.destreg__conditionalmod = conditional; 95 } 96 97 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode ) 98 { 99 p->current->header.access_mode = access_mode; 100 } 101 102 void 103 brw_set_compression_control(struct brw_compile *p, 104 enum brw_compression compression_control) 105 { 106 p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED); 107 108 if (p->brw->intel.gen >= 6) { 109 /* Since we don't use the 32-wide support in gen6, we translate 110 * the pre-gen6 compression control here. 111 */ 112 switch (compression_control) { 113 case BRW_COMPRESSION_NONE: 114 /* This is the "use the first set of bits of dmask/vmask/arf 115 * according to execsize" option. 116 */ 117 p->current->header.compression_control = GEN6_COMPRESSION_1Q; 118 break; 119 case BRW_COMPRESSION_2NDHALF: 120 /* For 8-wide, this is "use the second set of 8 bits." */ 121 p->current->header.compression_control = GEN6_COMPRESSION_2Q; 122 break; 123 case BRW_COMPRESSION_COMPRESSED: 124 /* For 16-wide instruction compression, use the first set of 16 bits 125 * since we don't do 32-wide dispatch. 126 */ 127 p->current->header.compression_control = GEN6_COMPRESSION_1H; 128 break; 129 default: 130 assert(!"not reached"); 131 p->current->header.compression_control = GEN6_COMPRESSION_1H; 132 break; 133 } 134 } else { 135 p->current->header.compression_control = compression_control; 136 } 137 } 138 139 void brw_set_mask_control( struct brw_compile *p, GLuint value ) 140 { 141 p->current->header.mask_control = value; 142 } 143 144 void brw_set_saturate( struct brw_compile *p, bool enable ) 145 { 146 p->current->header.saturate = enable; 147 } 148 149 void brw_set_acc_write_control(struct brw_compile *p, GLuint value) 150 { 151 if (p->brw->intel.gen >= 6) 152 p->current->header.acc_wr_control = value; 153 } 154 155 void brw_push_insn_state( struct brw_compile *p ) 156 { 157 assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]); 158 memcpy(p->current+1, p->current, sizeof(struct brw_instruction)); 159 p->compressed_stack[p->current - p->stack] = p->compressed; 160 p->current++; 161 } 162 163 void brw_pop_insn_state( struct brw_compile *p ) 164 { 165 assert(p->current != p->stack); 166 p->current--; 167 p->compressed = p->compressed_stack[p->current - p->stack]; 168 } 169 170 171 /*********************************************************************** 172 */ 173 void 174 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx) 175 { 176 p->brw = brw; 177 /* 178 * Set the initial instruction store array size to 1024, if found that 179 * isn't enough, then it will double the store size at brw_next_insn() 180 * until out of memory. 181 */ 182 p->store_size = 1024; 183 p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size); 184 p->nr_insn = 0; 185 p->current = p->stack; 186 p->compressed = false; 187 memset(p->current, 0, sizeof(p->current[0])); 188 189 p->mem_ctx = mem_ctx; 190 191 /* Some defaults? 192 */ 193 brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */ 194 brw_set_saturate(p, 0); 195 brw_set_compression_control(p, BRW_COMPRESSION_NONE); 196 brw_set_predicate_control_flag_value(p, 0xff); 197 198 /* Set up control flow stack */ 199 p->if_stack_depth = 0; 200 p->if_stack_array_size = 16; 201 p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size); 202 203 p->loop_stack_depth = 0; 204 p->loop_stack_array_size = 16; 205 p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size); 206 p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size); 207 } 208 209 210 const GLuint *brw_get_program( struct brw_compile *p, 211 GLuint *sz ) 212 { 213 GLuint i; 214 215 for (i = 0; i < 8; i++) 216 brw_NOP(p); 217 218 *sz = p->nr_insn * sizeof(struct brw_instruction); 219 return (const GLuint *)p->store; 220 } 221
