1 /****************************************************************************** 2 * 3 * Copyright (C) 1999-2012 Broadcom Corporation 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ******************************************************************************/ 18 19 /****************************************************************************** 20 * 21 * This file contains function of the HCIC unit to format and send HCI 22 * commands. 23 * 24 ******************************************************************************/ 25 26 #include "bt_target.h" 27 #include "bt_common.h" 28 #include "hcidefs.h" 29 #include "hcimsgs.h" 30 #include "hcidefs.h" 31 #include "btu.h" 32 33 #include <stddef.h> 34 #include <string.h> 35 36 #include "btm_int.h" /* Included for UIPC_* macro definitions */ 37 38 BOOLEAN btsnd_hcic_inquiry(const LAP inq_lap, UINT8 duration, UINT8 response_cnt) 39 { 40 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 41 UINT8 *pp = (UINT8 *)(p + 1); 42 43 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_INQUIRY; 44 p->offset = 0; 45 46 UINT16_TO_STREAM (pp, HCI_INQUIRY); 47 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_INQUIRY); 48 49 LAP_TO_STREAM (pp, inq_lap); 50 UINT8_TO_STREAM (pp, duration); 51 UINT8_TO_STREAM (pp, response_cnt); 52 53 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 54 return (TRUE); 55 } 56 57 BOOLEAN btsnd_hcic_inq_cancel(void) 58 { 59 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 60 UINT8 *pp = (UINT8 *)(p + 1); 61 62 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_INQ_CANCEL; 63 p->offset = 0; 64 UINT16_TO_STREAM (pp, HCI_INQUIRY_CANCEL); 65 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_INQ_CANCEL); 66 67 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 68 return (TRUE); 69 } 70 71 BOOLEAN btsnd_hcic_per_inq_mode (UINT16 max_period, UINT16 min_period, 72 const LAP inq_lap, UINT8 duration, UINT8 response_cnt) 73 { 74 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 75 UINT8 *pp = (UINT8 *)(p + 1); 76 77 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PER_INQ_MODE; 78 p->offset = 0; 79 80 UINT16_TO_STREAM (pp, HCI_PERIODIC_INQUIRY_MODE); 81 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_PER_INQ_MODE); 82 83 UINT16_TO_STREAM (pp, max_period); 84 UINT16_TO_STREAM (pp, min_period); 85 LAP_TO_STREAM (pp, inq_lap); 86 UINT8_TO_STREAM (pp, duration); 87 UINT8_TO_STREAM (pp, response_cnt); 88 89 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 90 return (TRUE); 91 } 92 93 BOOLEAN btsnd_hcic_exit_per_inq (void) 94 { 95 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 96 UINT8 *pp = (UINT8 *)(p + 1); 97 98 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXIT_PER_INQ; 99 p->offset = 0; 100 UINT16_TO_STREAM (pp, HCI_EXIT_PERIODIC_INQUIRY_MODE); 101 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_EXIT_PER_INQ); 102 103 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 104 return (TRUE); 105 } 106 107 108 BOOLEAN btsnd_hcic_create_conn(BD_ADDR dest, UINT16 packet_types, 109 UINT8 page_scan_rep_mode, UINT8 page_scan_mode, 110 UINT16 clock_offset, UINT8 allow_switch) 111 { 112 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 113 UINT8 *pp = (UINT8 *)(p + 1); 114 115 #ifndef BT_10A 116 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN; 117 #else 118 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN - 1; 119 #endif 120 p->offset = 0; 121 122 UINT16_TO_STREAM (pp, HCI_CREATE_CONNECTION); 123 #ifndef BT_10A 124 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CREATE_CONN); 125 #else 126 UINT8_TO_STREAM (pp, (HCIC_PARAM_SIZE_CREATE_CONN - 1)); 127 #endif 128 BDADDR_TO_STREAM (pp, dest); 129 UINT16_TO_STREAM (pp, packet_types); 130 UINT8_TO_STREAM (pp, page_scan_rep_mode); 131 UINT8_TO_STREAM (pp, page_scan_mode); 132 UINT16_TO_STREAM (pp, clock_offset); 133 #if !defined (BT_10A) 134 UINT8_TO_STREAM (pp, allow_switch); 135 #endif 136 btm_acl_paging (p, dest); 137 return (TRUE); 138 } 139 140 BOOLEAN btsnd_hcic_disconnect (UINT16 handle, UINT8 reason) 141 { 142 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 143 UINT8 *pp = (UINT8 *)(p + 1); 144 145 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT; 146 p->offset = 0; 147 148 UINT16_TO_STREAM (pp, HCI_DISCONNECT); 149 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_DISCONNECT); 150 UINT16_TO_STREAM (pp, handle); 151 UINT8_TO_STREAM (pp, reason); 152 153 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 154 return (TRUE); 155 } 156 157 #if BTM_SCO_INCLUDED == TRUE 158 BOOLEAN btsnd_hcic_add_SCO_conn (UINT16 handle, UINT16 packet_types) 159 { 160 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 161 UINT8 *pp = (UINT8 *)(p + 1); 162 163 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN; 164 p->offset = 0; 165 166 UINT16_TO_STREAM (pp, HCI_ADD_SCO_CONNECTION); 167 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_ADD_SCO_CONN); 168 169 UINT16_TO_STREAM (pp, handle); 170 UINT16_TO_STREAM (pp, packet_types); 171 172 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 173 return (TRUE); 174 } 175 #endif /* BTM_SCO_INCLUDED */ 176 177 BOOLEAN btsnd_hcic_create_conn_cancel(BD_ADDR dest) 178 { 179 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 180 UINT8 *pp = (UINT8 *)(p + 1); 181 182 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL; 183 p->offset = 0; 184 185 UINT16_TO_STREAM (pp, HCI_CREATE_CONNECTION_CANCEL); 186 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL); 187 188 BDADDR_TO_STREAM (pp, dest); 189 190 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 191 return (TRUE); 192 } 193 194 BOOLEAN btsnd_hcic_accept_conn (BD_ADDR dest, UINT8 role) 195 { 196 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 197 UINT8 *pp = (UINT8 *)(p + 1); 198 199 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_CONN; 200 p->offset = 0; 201 202 UINT16_TO_STREAM (pp, HCI_ACCEPT_CONNECTION_REQUEST); 203 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_ACCEPT_CONN); 204 BDADDR_TO_STREAM (pp, dest); 205 UINT8_TO_STREAM (pp, role); 206 207 208 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 209 return (TRUE); 210 } 211 212 BOOLEAN btsnd_hcic_reject_conn (BD_ADDR dest, UINT8 reason) 213 { 214 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 215 UINT8 *pp = (UINT8 *)(p + 1); 216 217 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN; 218 p->offset = 0; 219 220 UINT16_TO_STREAM (pp, HCI_REJECT_CONNECTION_REQUEST); 221 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_REJECT_CONN); 222 223 BDADDR_TO_STREAM (pp, dest); 224 UINT8_TO_STREAM (pp, reason); 225 226 227 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 228 return (TRUE); 229 } 230 231 BOOLEAN btsnd_hcic_link_key_req_reply (BD_ADDR bd_addr, LINK_KEY link_key) 232 { 233 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 234 UINT8 *pp = (UINT8 *)(p + 1); 235 236 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY; 237 p->offset = 0; 238 239 UINT16_TO_STREAM (pp, HCI_LINK_KEY_REQUEST_REPLY); 240 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY); 241 242 BDADDR_TO_STREAM (pp, bd_addr); 243 ARRAY16_TO_STREAM (pp, link_key); 244 245 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 246 return (TRUE); 247 } 248 249 BOOLEAN btsnd_hcic_link_key_neg_reply (BD_ADDR bd_addr) 250 { 251 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 252 UINT8 *pp = (UINT8 *)(p + 1); 253 254 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY; 255 p->offset = 0; 256 257 UINT16_TO_STREAM (pp, HCI_LINK_KEY_REQUEST_NEG_REPLY); 258 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY); 259 260 BDADDR_TO_STREAM (pp, bd_addr); 261 262 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 263 return (TRUE); 264 } 265 266 BOOLEAN btsnd_hcic_pin_code_req_reply (BD_ADDR bd_addr, UINT8 pin_code_len, 267 PIN_CODE pin_code) 268 { 269 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 270 UINT8 *pp = (UINT8 *)(p + 1); 271 int i; 272 273 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY; 274 p->offset = 0; 275 276 UINT16_TO_STREAM (pp, HCI_PIN_CODE_REQUEST_REPLY); 277 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY); 278 279 BDADDR_TO_STREAM (pp, bd_addr); 280 UINT8_TO_STREAM (pp, pin_code_len); 281 282 for (i = 0; i < pin_code_len; i++) 283 *pp++ = *pin_code++; 284 285 for (; i < PIN_CODE_LEN; i++) 286 *pp++ = 0; 287 288 289 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 290 return (TRUE); 291 } 292 293 BOOLEAN btsnd_hcic_pin_code_neg_reply (BD_ADDR bd_addr) 294 { 295 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 296 UINT8 *pp = (UINT8 *)(p + 1); 297 298 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY; 299 p->offset = 0; 300 301 UINT16_TO_STREAM (pp, HCI_PIN_CODE_REQUEST_NEG_REPLY); 302 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY); 303 304 BDADDR_TO_STREAM (pp, bd_addr); 305 306 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 307 return (TRUE); 308 } 309 310 BOOLEAN btsnd_hcic_change_conn_type (UINT16 handle, UINT16 packet_types) 311 { 312 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 313 UINT8 *pp = (UINT8 *)(p + 1); 314 315 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE; 316 p->offset = 0; 317 318 UINT16_TO_STREAM (pp, HCI_CHANGE_CONN_PACKET_TYPE); 319 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE); 320 321 UINT16_TO_STREAM (pp, handle); 322 UINT16_TO_STREAM (pp, packet_types); 323 324 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 325 return (TRUE); 326 } 327 328 BOOLEAN btsnd_hcic_auth_request (UINT16 handle) 329 { 330 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 331 UINT8 *pp = (UINT8 *)(p + 1); 332 333 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 334 p->offset = 0; 335 336 UINT16_TO_STREAM (pp, HCI_AUTHENTICATION_REQUESTED); 337 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 338 339 UINT16_TO_STREAM (pp, handle); 340 341 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 342 return (TRUE); 343 } 344 345 BOOLEAN btsnd_hcic_set_conn_encrypt (UINT16 handle, BOOLEAN enable) 346 { 347 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 348 UINT8 *pp = (UINT8 *)(p + 1); 349 350 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT; 351 p->offset = 0; 352 353 UINT16_TO_STREAM (pp, HCI_SET_CONN_ENCRYPTION); 354 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT); 355 356 UINT16_TO_STREAM (pp, handle); 357 UINT8_TO_STREAM (pp, enable); 358 359 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 360 return (TRUE); 361 } 362 363 BOOLEAN btsnd_hcic_rmt_name_req (BD_ADDR bd_addr, UINT8 page_scan_rep_mode, 364 UINT8 page_scan_mode, UINT16 clock_offset) 365 { 366 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 367 UINT8 *pp = (UINT8 *)(p + 1); 368 369 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_NAME_REQ; 370 p->offset = 0; 371 372 UINT16_TO_STREAM (pp, HCI_RMT_NAME_REQUEST); 373 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_RMT_NAME_REQ); 374 375 BDADDR_TO_STREAM (pp, bd_addr); 376 UINT8_TO_STREAM (pp, page_scan_rep_mode); 377 UINT8_TO_STREAM (pp, page_scan_mode); 378 UINT16_TO_STREAM (pp, clock_offset); 379 380 btm_acl_paging (p, bd_addr); 381 return (TRUE); 382 } 383 384 BOOLEAN btsnd_hcic_rmt_name_req_cancel (BD_ADDR bd_addr) 385 { 386 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 387 UINT8 *pp = (UINT8 *)(p + 1); 388 389 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL; 390 p->offset = 0; 391 392 UINT16_TO_STREAM (pp, HCI_RMT_NAME_REQUEST_CANCEL); 393 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL); 394 395 BDADDR_TO_STREAM (pp, bd_addr); 396 397 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 398 return (TRUE); 399 } 400 401 BOOLEAN btsnd_hcic_rmt_features_req (UINT16 handle) 402 { 403 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 404 UINT8 *pp = (UINT8 *)(p + 1); 405 406 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 407 p->offset = 0; 408 409 UINT16_TO_STREAM (pp, HCI_READ_RMT_FEATURES); 410 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 411 412 UINT16_TO_STREAM (pp, handle); 413 414 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 415 return (TRUE); 416 } 417 418 BOOLEAN btsnd_hcic_rmt_ext_features (UINT16 handle, UINT8 page_num) 419 { 420 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 421 UINT8 *pp = (UINT8 *)(p + 1); 422 423 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES; 424 p->offset = 0; 425 426 UINT16_TO_STREAM (pp, HCI_READ_RMT_EXT_FEATURES); 427 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES); 428 429 UINT16_TO_STREAM (pp, handle); 430 UINT8_TO_STREAM (pp, page_num); 431 432 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 433 return (TRUE); 434 } 435 436 BOOLEAN btsnd_hcic_rmt_ver_req (UINT16 handle) 437 { 438 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 439 UINT8 *pp = (UINT8 *)(p + 1); 440 441 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 442 p->offset = 0; 443 444 UINT16_TO_STREAM (pp, HCI_READ_RMT_VERSION_INFO); 445 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 446 447 UINT16_TO_STREAM (pp, handle); 448 449 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 450 return (TRUE); 451 } 452 453 BOOLEAN btsnd_hcic_read_rmt_clk_offset (UINT16 handle) 454 { 455 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 456 UINT8 *pp = (UINT8 *)(p + 1); 457 458 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 459 p->offset = 0; 460 461 UINT16_TO_STREAM (pp, HCI_READ_RMT_CLOCK_OFFSET); 462 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 463 464 UINT16_TO_STREAM (pp, handle); 465 466 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 467 return (TRUE); 468 } 469 470 BOOLEAN btsnd_hcic_read_lmp_handle (UINT16 handle) 471 { 472 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 473 UINT8 *pp = (UINT8 *)(p + 1); 474 475 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 476 p->offset = 0; 477 478 UINT16_TO_STREAM (pp, HCI_READ_LMP_HANDLE); 479 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 480 481 UINT16_TO_STREAM (pp, handle); 482 483 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 484 return (TRUE); 485 } 486 487 BOOLEAN btsnd_hcic_setup_esco_conn (UINT16 handle, UINT32 tx_bw, 488 UINT32 rx_bw, UINT16 max_latency, UINT16 voice, 489 UINT8 retrans_effort, UINT16 packet_types) 490 { 491 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 492 UINT8 *pp = (UINT8 *)(p + 1); 493 494 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO; 495 p->offset = 0; 496 497 UINT16_TO_STREAM (pp, HCI_SETUP_ESCO_CONNECTION); 498 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_SETUP_ESCO); 499 500 UINT16_TO_STREAM (pp, handle); 501 UINT32_TO_STREAM (pp, tx_bw); 502 UINT32_TO_STREAM (pp, rx_bw); 503 UINT16_TO_STREAM (pp, max_latency); 504 UINT16_TO_STREAM (pp, voice); 505 UINT8_TO_STREAM (pp, retrans_effort); 506 UINT16_TO_STREAM (pp, packet_types); 507 508 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 509 return (TRUE); 510 } 511 512 BOOLEAN btsnd_hcic_accept_esco_conn (BD_ADDR bd_addr, UINT32 tx_bw, 513 UINT32 rx_bw, UINT16 max_latency, 514 UINT16 content_fmt, UINT8 retrans_effort, 515 UINT16 packet_types) 516 { 517 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 518 UINT8 *pp = (UINT8 *)(p + 1); 519 520 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO; 521 p->offset = 0; 522 523 UINT16_TO_STREAM (pp, HCI_ACCEPT_ESCO_CONNECTION); 524 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_ACCEPT_ESCO); 525 526 BDADDR_TO_STREAM (pp, bd_addr); 527 UINT32_TO_STREAM (pp, tx_bw); 528 UINT32_TO_STREAM (pp, rx_bw); 529 UINT16_TO_STREAM (pp, max_latency); 530 UINT16_TO_STREAM (pp, content_fmt); 531 UINT8_TO_STREAM (pp, retrans_effort); 532 UINT16_TO_STREAM (pp, packet_types); 533 534 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 535 return (TRUE); 536 } 537 538 BOOLEAN btsnd_hcic_reject_esco_conn (BD_ADDR bd_addr, UINT8 reason) 539 { 540 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 541 UINT8 *pp = (UINT8 *)(p + 1); 542 543 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO; 544 p->offset = 0; 545 546 UINT16_TO_STREAM (pp, HCI_REJECT_ESCO_CONNECTION); 547 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_REJECT_ESCO); 548 549 BDADDR_TO_STREAM (pp, bd_addr); 550 UINT8_TO_STREAM (pp, reason); 551 552 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 553 return (TRUE); 554 } 555 556 BOOLEAN btsnd_hcic_hold_mode (UINT16 handle, UINT16 max_hold_period, 557 UINT16 min_hold_period) 558 { 559 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 560 UINT8 *pp = (UINT8 *)(p + 1); 561 562 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE; 563 p->offset = 0; 564 565 UINT16_TO_STREAM (pp, HCI_HOLD_MODE); 566 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_HOLD_MODE); 567 568 UINT16_TO_STREAM (pp, handle); 569 UINT16_TO_STREAM (pp, max_hold_period); 570 UINT16_TO_STREAM (pp, min_hold_period); 571 572 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 573 return (TRUE); 574 } 575 576 BOOLEAN btsnd_hcic_sniff_mode (UINT16 handle, UINT16 max_sniff_period, 577 UINT16 min_sniff_period, UINT16 sniff_attempt, 578 UINT16 sniff_timeout) 579 { 580 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 581 UINT8 *pp = (UINT8 *)(p + 1); 582 583 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE; 584 p->offset = 0; 585 586 UINT16_TO_STREAM (pp, HCI_SNIFF_MODE); 587 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_SNIFF_MODE); 588 589 UINT16_TO_STREAM (pp, handle); 590 UINT16_TO_STREAM (pp, max_sniff_period); 591 UINT16_TO_STREAM (pp, min_sniff_period); 592 UINT16_TO_STREAM (pp, sniff_attempt); 593 UINT16_TO_STREAM (pp, sniff_timeout); 594 595 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 596 return (TRUE); 597 } 598 599 BOOLEAN btsnd_hcic_exit_sniff_mode (UINT16 handle) 600 { 601 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 602 UINT8 *pp = (UINT8 *)(p + 1); 603 604 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 605 p->offset = 0; 606 607 UINT16_TO_STREAM (pp, HCI_EXIT_SNIFF_MODE); 608 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 609 610 UINT16_TO_STREAM (pp, handle); 611 612 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 613 return TRUE; 614 } 615 616 BOOLEAN btsnd_hcic_park_mode (UINT16 handle, UINT16 beacon_max_interval, 617 UINT16 beacon_min_interval) 618 { 619 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 620 UINT8 *pp = (UINT8 *)(p + 1); 621 622 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE; 623 p->offset = 0; 624 625 UINT16_TO_STREAM (pp, HCI_PARK_MODE); 626 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_PARK_MODE); 627 628 UINT16_TO_STREAM (pp, handle); 629 UINT16_TO_STREAM (pp, beacon_max_interval); 630 UINT16_TO_STREAM (pp, beacon_min_interval); 631 632 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 633 return (TRUE); 634 } 635 636 BOOLEAN btsnd_hcic_exit_park_mode (UINT16 handle) 637 { 638 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 639 UINT8 *pp = (UINT8 *)(p + 1); 640 641 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 642 p->offset = 0; 643 644 UINT16_TO_STREAM (pp, HCI_EXIT_PARK_MODE); 645 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 646 647 UINT16_TO_STREAM (pp, handle); 648 649 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 650 return TRUE; 651 } 652 653 BOOLEAN btsnd_hcic_qos_setup (UINT16 handle, UINT8 flags, UINT8 service_type, 654 UINT32 token_rate, UINT32 peak, UINT32 latency, 655 UINT32 delay_var) 656 { 657 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 658 UINT8 *pp = (UINT8 *)(p + 1); 659 660 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_QOS_SETUP; 661 p->offset = 0; 662 663 UINT16_TO_STREAM (pp, HCI_QOS_SETUP); 664 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_QOS_SETUP); 665 666 UINT16_TO_STREAM (pp, handle); 667 UINT8_TO_STREAM (pp, flags); 668 UINT8_TO_STREAM (pp, service_type); 669 UINT32_TO_STREAM (pp, token_rate); 670 UINT32_TO_STREAM (pp, peak); 671 UINT32_TO_STREAM (pp, latency); 672 UINT32_TO_STREAM (pp, delay_var); 673 674 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 675 return (TRUE); 676 } 677 678 BOOLEAN btsnd_hcic_switch_role (BD_ADDR bd_addr, UINT8 role) 679 { 680 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 681 UINT8 *pp = (UINT8 *)(p + 1); 682 683 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE; 684 p->offset = 0; 685 686 UINT16_TO_STREAM (pp, HCI_SWITCH_ROLE); 687 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_SWITCH_ROLE); 688 689 BDADDR_TO_STREAM (pp, bd_addr); 690 UINT8_TO_STREAM (pp, role); 691 692 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 693 return (TRUE); 694 } 695 696 BOOLEAN btsnd_hcic_write_policy_set (UINT16 handle, UINT16 settings) 697 { 698 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 699 UINT8 *pp = (UINT8 *)(p + 1); 700 701 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET; 702 p->offset = 0; 703 UINT16_TO_STREAM (pp, HCI_WRITE_POLICY_SETTINGS); 704 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET); 705 706 UINT16_TO_STREAM (pp, handle); 707 UINT16_TO_STREAM (pp, settings); 708 709 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 710 return (TRUE); 711 } 712 713 BOOLEAN btsnd_hcic_write_def_policy_set (UINT16 settings) 714 { 715 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 716 UINT8 *pp = (UINT8 *)(p + 1); 717 718 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET; 719 p->offset = 0; 720 UINT16_TO_STREAM (pp, HCI_WRITE_DEF_POLICY_SETTINGS); 721 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET); 722 723 UINT16_TO_STREAM (pp, settings); 724 725 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 726 return (TRUE); 727 } 728 729 BOOLEAN btsnd_hcic_set_event_filter (UINT8 filt_type, UINT8 filt_cond_type, 730 UINT8 *filt_cond, UINT8 filt_cond_len) 731 { 732 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 733 UINT8 *pp = (UINT8 *)(p + 1); 734 735 p->offset = 0; 736 737 UINT16_TO_STREAM (pp, HCI_SET_EVENT_FILTER); 738 739 if (filt_type) 740 { 741 p->len = (UINT16)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len); 742 UINT8_TO_STREAM (pp, (UINT8)(2 + filt_cond_len)); 743 744 UINT8_TO_STREAM (pp, filt_type); 745 UINT8_TO_STREAM (pp, filt_cond_type); 746 747 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) 748 { 749 DEVCLASS_TO_STREAM (pp, filt_cond); 750 filt_cond += DEV_CLASS_LEN; 751 DEVCLASS_TO_STREAM (pp, filt_cond); 752 filt_cond += DEV_CLASS_LEN; 753 754 filt_cond_len -= (2 * DEV_CLASS_LEN); 755 } 756 else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) 757 { 758 BDADDR_TO_STREAM (pp, filt_cond); 759 filt_cond += BD_ADDR_LEN; 760 761 filt_cond_len -= BD_ADDR_LEN; 762 } 763 764 if (filt_cond_len) 765 ARRAY_TO_STREAM (pp, filt_cond, filt_cond_len); 766 } 767 else 768 { 769 p->len = (UINT16)(HCIC_PREAMBLE_SIZE + 1); 770 UINT8_TO_STREAM (pp, 1); 771 772 UINT8_TO_STREAM (pp, filt_type); 773 } 774 775 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 776 return (TRUE); 777 } 778 779 BOOLEAN btsnd_hcic_write_pin_type (UINT8 type) 780 { 781 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 782 UINT8 *pp = (UINT8 *)(p + 1); 783 784 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 785 p->offset = 0; 786 787 UINT16_TO_STREAM (pp, HCI_WRITE_PIN_TYPE); 788 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 789 790 UINT8_TO_STREAM (pp, type); 791 792 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 793 return (TRUE); 794 } 795 796 BOOLEAN btsnd_hcic_delete_stored_key (BD_ADDR bd_addr, BOOLEAN delete_all_flag) 797 { 798 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 799 UINT8 *pp = (UINT8 *)(p + 1); 800 801 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY; 802 p->offset = 0; 803 804 UINT16_TO_STREAM (pp, HCI_DELETE_STORED_LINK_KEY); 805 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY); 806 807 BDADDR_TO_STREAM (pp, bd_addr); 808 UINT8_TO_STREAM (pp, delete_all_flag); 809 810 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 811 return (TRUE); 812 } 813 814 BOOLEAN btsnd_hcic_change_name (BD_NAME name) 815 { 816 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 817 UINT8 *pp = (UINT8 *)(p + 1); 818 UINT16 len = strlen((char *)name) + 1; 819 820 memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME); 821 822 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME; 823 p->offset = 0; 824 825 UINT16_TO_STREAM (pp, HCI_CHANGE_LOCAL_NAME); 826 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CHANGE_NAME); 827 828 if (len > HCIC_PARAM_SIZE_CHANGE_NAME) 829 len = HCIC_PARAM_SIZE_CHANGE_NAME; 830 831 ARRAY_TO_STREAM (pp, name, len); 832 833 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 834 return (TRUE); 835 } 836 837 BOOLEAN btsnd_hcic_read_name (void) 838 { 839 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 840 UINT8 *pp = (UINT8 *)(p + 1); 841 842 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 843 p->offset = 0; 844 845 UINT16_TO_STREAM (pp, HCI_READ_LOCAL_NAME); 846 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_READ_CMD); 847 848 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 849 return (TRUE); 850 } 851 852 BOOLEAN btsnd_hcic_write_page_tout (UINT16 timeout) 853 { 854 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 855 UINT8 *pp = (UINT8 *)(p + 1); 856 857 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 858 p->offset = 0; 859 860 UINT16_TO_STREAM (pp, HCI_WRITE_PAGE_TOUT); 861 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 862 863 UINT16_TO_STREAM (pp, timeout); 864 865 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 866 return (TRUE); 867 } 868 869 BOOLEAN btsnd_hcic_write_scan_enable (UINT8 flag) 870 { 871 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 872 UINT8 *pp = (UINT8 *)(p + 1); 873 874 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 875 p->offset = 0; 876 877 UINT16_TO_STREAM (pp, HCI_WRITE_SCAN_ENABLE); 878 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 879 880 UINT8_TO_STREAM (pp, flag); 881 882 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 883 return (TRUE); 884 } 885 886 BOOLEAN btsnd_hcic_write_pagescan_cfg(UINT16 interval, UINT16 window) 887 { 888 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 889 UINT8 *pp = (UINT8 *)(p + 1); 890 891 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG; 892 p->offset = 0; 893 894 UINT16_TO_STREAM (pp, HCI_WRITE_PAGESCAN_CFG); 895 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG); 896 897 UINT16_TO_STREAM (pp, interval); 898 UINT16_TO_STREAM (pp, window); 899 900 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 901 return (TRUE); 902 } 903 904 BOOLEAN btsnd_hcic_write_inqscan_cfg(UINT16 interval, UINT16 window) 905 { 906 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 907 UINT8 *pp = (UINT8 *)(p + 1); 908 909 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG; 910 p->offset = 0; 911 912 UINT16_TO_STREAM (pp, HCI_WRITE_INQUIRYSCAN_CFG); 913 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG); 914 915 UINT16_TO_STREAM (pp, interval); 916 UINT16_TO_STREAM (pp, window); 917 918 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 919 return (TRUE); 920 } 921 922 BOOLEAN btsnd_hcic_write_auth_enable (UINT8 flag) 923 { 924 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 925 UINT8 *pp = (UINT8 *)(p + 1); 926 927 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 928 p->offset = 0; 929 930 UINT16_TO_STREAM (pp, HCI_WRITE_AUTHENTICATION_ENABLE); 931 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 932 933 UINT8_TO_STREAM (pp, flag); 934 935 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 936 return (TRUE); 937 } 938 939 BOOLEAN btsnd_hcic_write_dev_class(DEV_CLASS dev_class) 940 { 941 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 942 UINT8 *pp = (UINT8 *)(p + 1); 943 944 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3; 945 p->offset = 0; 946 947 UINT16_TO_STREAM (pp, HCI_WRITE_CLASS_OF_DEVICE); 948 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM3); 949 950 DEVCLASS_TO_STREAM (pp, dev_class); 951 952 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 953 return (TRUE); 954 } 955 956 BOOLEAN btsnd_hcic_write_voice_settings(UINT16 flags) 957 { 958 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 959 UINT8 *pp = (UINT8 *)(p + 1); 960 961 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 962 p->offset = 0; 963 964 UINT16_TO_STREAM (pp, HCI_WRITE_VOICE_SETTINGS); 965 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 966 967 UINT16_TO_STREAM (pp, flags); 968 969 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 970 return (TRUE); 971 } 972 973 BOOLEAN btsnd_hcic_write_auto_flush_tout (UINT16 handle, UINT16 tout) 974 { 975 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 976 UINT8 *pp = (UINT8 *)(p + 1); 977 978 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTO_FLUSH_TOUT; 979 p->offset = 0; 980 981 UINT16_TO_STREAM (pp, HCI_WRITE_AUTO_FLUSH_TOUT); 982 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_AUTO_FLUSH_TOUT); 983 984 UINT16_TO_STREAM (pp, handle); 985 UINT16_TO_STREAM (pp, tout); 986 987 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 988 return (TRUE); 989 } 990 991 BOOLEAN btsnd_hcic_read_tx_power (UINT16 handle, UINT8 type) 992 { 993 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 994 UINT8 *pp = (UINT8 *)(p + 1); 995 996 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER; 997 p->offset = 0; 998 999 UINT16_TO_STREAM (pp, HCI_READ_TRANSMIT_POWER_LEVEL); 1000 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_READ_TX_POWER); 1001 1002 UINT16_TO_STREAM (pp, handle); 1003 UINT8_TO_STREAM (pp, type); 1004 1005 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1006 return (TRUE); 1007 } 1008 1009 BOOLEAN btsnd_hcic_host_num_xmitted_pkts (UINT8 num_handles, UINT16 *handle, 1010 UINT16 *num_pkts) 1011 { 1012 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1013 UINT8 *pp = (UINT8 *)(p + 1); 1014 1015 p->len = HCIC_PREAMBLE_SIZE + 1 + (num_handles * 4); 1016 p->offset = 0; 1017 1018 UINT16_TO_STREAM (pp, HCI_HOST_NUM_PACKETS_DONE); 1019 UINT8_TO_STREAM (pp, p->len - HCIC_PREAMBLE_SIZE); 1020 1021 UINT8_TO_STREAM (pp, num_handles); 1022 1023 for (int i = 0; i < num_handles; i++) { 1024 UINT16_TO_STREAM(pp, handle[i]); 1025 UINT16_TO_STREAM(pp, num_pkts[i]); 1026 } 1027 1028 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1029 return (TRUE); 1030 } 1031 1032 BOOLEAN btsnd_hcic_write_link_super_tout (UINT8 local_controller_id, UINT16 handle, UINT16 timeout) 1033 { 1034 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1035 UINT8 *pp = (UINT8 *)(p + 1); 1036 1037 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT; 1038 p->offset = 0; 1039 1040 UINT16_TO_STREAM (pp, HCI_WRITE_LINK_SUPER_TOUT); 1041 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT); 1042 1043 UINT16_TO_STREAM (pp, handle); 1044 UINT16_TO_STREAM (pp, timeout); 1045 1046 btu_hcif_send_cmd (local_controller_id, p); 1047 return (TRUE); 1048 } 1049 1050 BOOLEAN btsnd_hcic_write_cur_iac_lap (UINT8 num_cur_iac, LAP * const iac_lap) 1051 { 1052 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1053 UINT8 *pp = (UINT8 *)(p + 1); 1054 1055 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac); 1056 p->offset = 0; 1057 1058 UINT16_TO_STREAM (pp, HCI_WRITE_CURRENT_IAC_LAP); 1059 UINT8_TO_STREAM (pp, p->len - HCIC_PREAMBLE_SIZE); 1060 1061 UINT8_TO_STREAM (pp, num_cur_iac); 1062 1063 for (int i = 0; i < num_cur_iac; i++) 1064 LAP_TO_STREAM (pp, iac_lap[i]); 1065 1066 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1067 return (TRUE); 1068 } 1069 1070 /****************************************** 1071 ** Lisbon Features 1072 *******************************************/ 1073 #if BTM_SSR_INCLUDED == TRUE 1074 1075 BOOLEAN btsnd_hcic_sniff_sub_rate(UINT16 handle, UINT16 max_lat, 1076 UINT16 min_remote_lat, UINT16 min_local_lat) 1077 { 1078 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1079 UINT8 *pp = (UINT8 *)(p + 1); 1080 1081 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE; 1082 p->offset = 0; 1083 1084 UINT16_TO_STREAM (pp, HCI_SNIFF_SUB_RATE); 1085 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE); 1086 1087 UINT16_TO_STREAM (pp, handle); 1088 UINT16_TO_STREAM (pp, max_lat); 1089 UINT16_TO_STREAM (pp, min_remote_lat); 1090 UINT16_TO_STREAM (pp, min_local_lat); 1091 1092 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1093 return (TRUE); 1094 } 1095 #endif /* BTM_SSR_INCLUDED */ 1096 1097 /**** Extended Inquiry Response Commands ****/ 1098 void btsnd_hcic_write_ext_inquiry_response (void *buffer, UINT8 fec_req) 1099 { 1100 BT_HDR *p = (BT_HDR *)buffer; 1101 UINT8 *pp = (UINT8 *)(p + 1); 1102 1103 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP; 1104 p->offset = 0; 1105 1106 UINT16_TO_STREAM (pp, HCI_WRITE_EXT_INQ_RESPONSE); 1107 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_EXT_INQ_RESP); 1108 1109 UINT8_TO_STREAM (pp, fec_req); 1110 1111 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1112 } 1113 1114 BOOLEAN btsnd_hcic_io_cap_req_reply (BD_ADDR bd_addr, UINT8 capability, 1115 UINT8 oob_present, UINT8 auth_req) 1116 { 1117 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1118 UINT8 *pp = (UINT8 *)(p + 1); 1119 1120 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP; 1121 p->offset = 0; 1122 1123 UINT16_TO_STREAM (pp, HCI_IO_CAPABILITY_REQUEST_REPLY); 1124 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_IO_CAP_RESP); 1125 1126 BDADDR_TO_STREAM (pp, bd_addr); 1127 UINT8_TO_STREAM (pp, capability); 1128 UINT8_TO_STREAM (pp, oob_present); 1129 UINT8_TO_STREAM (pp, auth_req); 1130 1131 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1132 return (TRUE); 1133 } 1134 1135 BOOLEAN btsnd_hcic_io_cap_req_neg_reply (BD_ADDR bd_addr, UINT8 err_code) 1136 { 1137 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1138 UINT8 *pp = (UINT8 *)(p + 1); 1139 1140 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY; 1141 p->offset = 0; 1142 1143 UINT16_TO_STREAM (pp, HCI_IO_CAP_REQ_NEG_REPLY); 1144 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY); 1145 1146 BDADDR_TO_STREAM (pp, bd_addr); 1147 UINT8_TO_STREAM (pp, err_code); 1148 1149 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1150 return (TRUE); 1151 } 1152 1153 BOOLEAN btsnd_hcic_read_local_oob_data (void) 1154 { 1155 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1156 UINT8 *pp = (UINT8 *)(p + 1); 1157 1158 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB; 1159 p->offset = 0; 1160 1161 UINT16_TO_STREAM (pp, HCI_READ_LOCAL_OOB_DATA); 1162 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_R_LOCAL_OOB); 1163 1164 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1165 return (TRUE); 1166 } 1167 1168 BOOLEAN btsnd_hcic_user_conf_reply (BD_ADDR bd_addr, BOOLEAN is_yes) 1169 { 1170 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1171 UINT8 *pp = (UINT8 *)(p + 1); 1172 1173 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY; 1174 p->offset = 0; 1175 1176 if (!is_yes) 1177 { 1178 /* Negative reply */ 1179 UINT16_TO_STREAM (pp, HCI_USER_CONF_VALUE_NEG_REPLY); 1180 } 1181 else 1182 { 1183 /* Confirmation */ 1184 UINT16_TO_STREAM (pp, HCI_USER_CONF_REQUEST_REPLY); 1185 } 1186 1187 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_UCONF_REPLY); 1188 1189 BDADDR_TO_STREAM (pp, bd_addr); 1190 1191 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1192 return (TRUE); 1193 } 1194 1195 BOOLEAN btsnd_hcic_user_passkey_reply (BD_ADDR bd_addr, UINT32 value) 1196 { 1197 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1198 UINT8 *pp = (UINT8 *)(p + 1); 1199 1200 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY; 1201 p->offset = 0; 1202 1203 UINT16_TO_STREAM (pp, HCI_USER_PASSKEY_REQ_REPLY); 1204 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_U_PKEY_REPLY); 1205 1206 BDADDR_TO_STREAM (pp, bd_addr); 1207 UINT32_TO_STREAM (pp, value); 1208 1209 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1210 return (TRUE); 1211 } 1212 1213 BOOLEAN btsnd_hcic_user_passkey_neg_reply (BD_ADDR bd_addr) 1214 { 1215 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1216 UINT8 *pp = (UINT8 *)(p + 1); 1217 1218 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY; 1219 p->offset = 0; 1220 1221 UINT16_TO_STREAM (pp, HCI_USER_PASSKEY_REQ_NEG_REPLY); 1222 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY); 1223 1224 BDADDR_TO_STREAM (pp, bd_addr); 1225 1226 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1227 return (TRUE); 1228 } 1229 1230 BOOLEAN btsnd_hcic_rem_oob_reply (BD_ADDR bd_addr, UINT8 *p_c, UINT8 *p_r) 1231 { 1232 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1233 UINT8 *pp = (UINT8 *)(p + 1); 1234 1235 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY; 1236 p->offset = 0; 1237 1238 UINT16_TO_STREAM (pp, HCI_REM_OOB_DATA_REQ_REPLY); 1239 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_REM_OOB_REPLY); 1240 1241 BDADDR_TO_STREAM (pp, bd_addr); 1242 ARRAY16_TO_STREAM (pp, p_c); 1243 ARRAY16_TO_STREAM (pp, p_r); 1244 1245 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1246 return (TRUE); 1247 } 1248 1249 BOOLEAN btsnd_hcic_rem_oob_neg_reply (BD_ADDR bd_addr) 1250 { 1251 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1252 UINT8 *pp = (UINT8 *)(p + 1); 1253 1254 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY; 1255 p->offset = 0; 1256 1257 UINT16_TO_STREAM (pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY); 1258 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY); 1259 1260 BDADDR_TO_STREAM (pp, bd_addr); 1261 1262 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1263 return (TRUE); 1264 } 1265 1266 1267 BOOLEAN btsnd_hcic_read_inq_tx_power (void) 1268 { 1269 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1270 UINT8 *pp = (UINT8 *)(p + 1); 1271 1272 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_TX_POWER; 1273 p->offset = 0; 1274 1275 UINT16_TO_STREAM (pp, HCI_READ_INQ_TX_POWER_LEVEL); 1276 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_R_TX_POWER); 1277 1278 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1279 return (TRUE); 1280 } 1281 1282 BOOLEAN btsnd_hcic_send_keypress_notif (BD_ADDR bd_addr, UINT8 notif) 1283 { 1284 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1285 UINT8 *pp = (UINT8 *)(p + 1); 1286 1287 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF; 1288 p->offset = 0; 1289 1290 UINT16_TO_STREAM (pp, HCI_SEND_KEYPRESS_NOTIF); 1291 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF); 1292 1293 BDADDR_TO_STREAM (pp, bd_addr); 1294 UINT8_TO_STREAM (pp, notif); 1295 1296 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1297 return (TRUE); 1298 } 1299 1300 /**** end of Simple Pairing Commands ****/ 1301 1302 #if L2CAP_NON_FLUSHABLE_PB_INCLUDED == TRUE 1303 BOOLEAN btsnd_hcic_enhanced_flush (UINT16 handle, UINT8 packet_type) 1304 { 1305 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1306 UINT8 *pp = (UINT8 *)(p + 1); 1307 1308 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENHANCED_FLUSH; 1309 p->offset = 0; 1310 UINT16_TO_STREAM (pp, HCI_ENHANCED_FLUSH); 1311 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_ENHANCED_FLUSH); 1312 1313 UINT16_TO_STREAM (pp, handle); 1314 UINT8_TO_STREAM (pp, packet_type); 1315 1316 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1317 return (TRUE); 1318 } 1319 #endif 1320 1321 /************************* 1322 ** End of Lisbon Commands 1323 **************************/ 1324 1325 BOOLEAN btsnd_hcic_get_link_quality (UINT16 handle) 1326 { 1327 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1328 UINT8 *pp = (UINT8 *)(p + 1); 1329 1330 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1331 p->offset = 0; 1332 1333 UINT16_TO_STREAM (pp, HCI_GET_LINK_QUALITY); 1334 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1335 1336 UINT16_TO_STREAM (pp, handle); 1337 1338 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1339 return (TRUE); 1340 } 1341 1342 BOOLEAN btsnd_hcic_read_rssi (UINT16 handle) 1343 { 1344 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1345 UINT8 *pp = (UINT8 *)(p + 1); 1346 1347 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1348 p->offset = 0; 1349 1350 UINT16_TO_STREAM (pp, HCI_READ_RSSI); 1351 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1352 1353 UINT16_TO_STREAM (pp, handle); 1354 1355 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1356 return (TRUE); 1357 } 1358 1359 BOOLEAN btsnd_hcic_enable_test_mode (void) 1360 { 1361 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1362 UINT8 *pp = (UINT8 *)(p + 1); 1363 1364 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 1365 p->offset = 0; 1366 1367 UINT16_TO_STREAM (pp, HCI_ENABLE_DEV_UNDER_TEST_MODE); 1368 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_READ_CMD); 1369 1370 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1371 return (TRUE); 1372 } 1373 1374 BOOLEAN btsnd_hcic_write_inqscan_type (UINT8 type) 1375 { 1376 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1377 UINT8 *pp = (UINT8 *)(p + 1); 1378 1379 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1380 p->offset = 0; 1381 1382 UINT16_TO_STREAM (pp, HCI_WRITE_INQSCAN_TYPE); 1383 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1384 1385 UINT8_TO_STREAM (pp, type); 1386 1387 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1388 return (TRUE); 1389 } 1390 1391 BOOLEAN btsnd_hcic_write_inquiry_mode (UINT8 mode) 1392 { 1393 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1394 UINT8 *pp = (UINT8 *)(p + 1); 1395 1396 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1397 p->offset = 0; 1398 1399 UINT16_TO_STREAM (pp, HCI_WRITE_INQUIRY_MODE); 1400 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1401 1402 UINT8_TO_STREAM (pp, mode); 1403 1404 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1405 return (TRUE); 1406 } 1407 1408 BOOLEAN btsnd_hcic_write_pagescan_type (UINT8 type) 1409 { 1410 BT_HDR *p = (BT_HDR *)osi_malloc(HCI_CMD_BUF_SIZE); 1411 UINT8 *pp = (UINT8 *)(p + 1); 1412 1413 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1414 p->offset = 0; 1415 1416 UINT16_TO_STREAM (pp, HCI_WRITE_PAGESCAN_TYPE); 1417 UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1418 1419 UINT8_TO_STREAM (pp, type); 1420 1421 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1422 return (TRUE); 1423 } 1424 1425 /* Must have room to store BT_HDR + max VSC length + callback pointer */ 1426 #if (HCI_CMD_BUF_SIZE < 268) 1427 #error "HCI_CMD_BUF_SIZE must be larger than 268" 1428 #endif 1429 1430 void btsnd_hcic_vendor_spec_cmd (void *buffer, UINT16 opcode, UINT8 len, 1431 UINT8 *p_data, void *p_cmd_cplt_cback) 1432 { 1433 BT_HDR *p = (BT_HDR *)buffer; 1434 UINT8 *pp = (UINT8 *)(p + 1); 1435 1436 p->len = HCIC_PREAMBLE_SIZE + len; 1437 p->offset = sizeof(void *); 1438 1439 *((void **)pp) = p_cmd_cplt_cback; /* Store command complete callback in buffer */ 1440 pp += sizeof(void *); /* Skip over callback pointer */ 1441 1442 UINT16_TO_STREAM (pp, HCI_GRP_VENDOR_SPECIFIC | opcode); 1443 UINT8_TO_STREAM (pp, len); 1444 ARRAY_TO_STREAM (pp, p_data, len); 1445 1446 btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p); 1447 } 1448
