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      1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #include "llvm/MC/MCSubtargetInfo.h"
     11 #include "llvm/ADT/StringRef.h"
     12 #include "llvm/ADT/Triple.h"
     13 #include "llvm/MC/MCInstrItineraries.h"
     14 #include "llvm/MC/SubtargetFeature.h"
     15 #include "llvm/Support/raw_ostream.h"
     16 #include <algorithm>
     17 
     18 using namespace llvm;
     19 
     20 static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
     21                                  ArrayRef<SubtargetFeatureKV> ProcDesc,
     22                                  ArrayRef<SubtargetFeatureKV> ProcFeatures) {
     23   SubtargetFeatures Features(FS);
     24   return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
     25 }
     26 
     27 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
     28   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
     29   if (!CPU.empty())
     30     CPUSchedModel = &getSchedModelForCPU(CPU);
     31   else
     32     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
     33 }
     34 
     35 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
     36   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
     37 }
     38 
     39 MCSubtargetInfo::MCSubtargetInfo(
     40     const Triple &TT, StringRef C, StringRef FS,
     41     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
     42     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
     43     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
     44     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
     45     : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
     46       ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
     47       ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
     48   InitMCProcessorInfo(CPU, FS);
     49 }
     50 
     51 /// ToggleFeature - Toggle a feature and returns the re-computed feature
     52 /// bits. This version does not change the implied bits.
     53 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
     54   FeatureBits.flip(FB);
     55   return FeatureBits;
     56 }
     57 
     58 FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
     59   FeatureBits ^= FB;
     60   return FeatureBits;
     61 }
     62 
     63 /// ToggleFeature - Toggle a feature and returns the re-computed feature
     64 /// bits. This version will also change all implied bits.
     65 FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
     66   SubtargetFeatures Features;
     67   FeatureBits = Features.ToggleFeature(FeatureBits, FS, ProcFeatures);
     68   return FeatureBits;
     69 }
     70 
     71 FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
     72   SubtargetFeatures Features;
     73   FeatureBits = Features.ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
     74   return FeatureBits;
     75 }
     76 
     77 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
     78   assert(ProcSchedModels && "Processor machine model not available!");
     79 
     80   size_t NumProcs = ProcDesc.size();
     81   assert(std::is_sorted(ProcSchedModels, ProcSchedModels+NumProcs,
     82                     [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
     83                       return strcmp(LHS.Key, RHS.Key) < 0;
     84                     }) &&
     85          "Processor machine model table is not sorted");
     86 
     87   // Find entry
     88   const SubtargetInfoKV *Found =
     89     std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, CPU);
     90   if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
     91     if (CPU != "help") // Don't error if the user asked for help.
     92       errs() << "'" << CPU
     93              << "' is not a recognized processor for this target"
     94              << " (ignoring processor)\n";
     95     return MCSchedModel::GetDefaultSchedModel();
     96   }
     97   assert(Found->Value && "Missing processor SchedModel value");
     98   return *(const MCSchedModel *)Found->Value;
     99 }
    100 
    101 InstrItineraryData
    102 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
    103   const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
    104   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
    105 }
    106 
    107 /// Initialize an InstrItineraryData instance.
    108 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
    109   InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
    110                                   ForwardingPaths);
    111 }
    112