1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Config/config.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/FileSystem.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include <string.h> 24 25 // Include the platform-specific parts of this class. 26 #ifdef LLVM_ON_UNIX 27 #include "Unix/Host.inc" 28 #endif 29 #ifdef LLVM_ON_WIN32 30 #include "Windows/Host.inc" 31 #endif 32 #ifdef _MSC_VER 33 #include <intrin.h> 34 #endif 35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 36 #include <mach/mach.h> 37 #include <mach/mach_host.h> 38 #include <mach/host_info.h> 39 #include <mach/machine.h> 40 #endif 41 42 #define DEBUG_TYPE "host-detection" 43 44 //===----------------------------------------------------------------------===// 45 // 46 // Implementations of the CPU detection routines 47 // 48 //===----------------------------------------------------------------------===// 49 50 using namespace llvm; 51 52 #if defined(__linux__) 53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) { 54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting 55 // memory buffer because the 'file' has 0 size (it can be read from only 56 // as a stream). 57 58 int FD; 59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD); 60 if (EC) { 61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n"); 62 return -1; 63 } 64 int Ret = read(FD, Buf, Size); 65 int CloseStatus = close(FD); 66 if (CloseStatus) 67 return -1; 68 return Ret; 69 } 70 #endif 71 72 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 73 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 74 75 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the 76 /// specified arguments. If we can't run cpuid on the host, return true. 77 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 78 unsigned *rECX, unsigned *rEDX) { 79 #if defined(__GNUC__) || defined(__clang__) 80 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 81 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 82 asm ("movq\t%%rbx, %%rsi\n\t" 83 "cpuid\n\t" 84 "xchgq\t%%rbx, %%rsi\n\t" 85 : "=a" (*rEAX), 86 "=S" (*rEBX), 87 "=c" (*rECX), 88 "=d" (*rEDX) 89 : "a" (value)); 90 return false; 91 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 92 asm ("movl\t%%ebx, %%esi\n\t" 93 "cpuid\n\t" 94 "xchgl\t%%ebx, %%esi\n\t" 95 : "=a" (*rEAX), 96 "=S" (*rEBX), 97 "=c" (*rECX), 98 "=d" (*rEDX) 99 : "a" (value)); 100 return false; 101 // pedantic #else returns to appease -Wunreachable-code (so we don't generate 102 // postprocessed code that looks like "return true; return false;") 103 #else 104 return true; 105 #endif 106 #elif defined(_MSC_VER) 107 // The MSVC intrinsic is portable across x86 and x64. 108 int registers[4]; 109 __cpuid(registers, value); 110 *rEAX = registers[0]; 111 *rEBX = registers[1]; 112 *rECX = registers[2]; 113 *rEDX = registers[3]; 114 return false; 115 #else 116 return true; 117 #endif 118 } 119 120 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the 121 /// 4 values in the specified arguments. If we can't run cpuid on the host, 122 /// return true. 123 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 124 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 125 unsigned *rEDX) { 126 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 127 #if defined(__GNUC__) 128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually. 129 asm ("movq\t%%rbx, %%rsi\n\t" 130 "cpuid\n\t" 131 "xchgq\t%%rbx, %%rsi\n\t" 132 : "=a" (*rEAX), 133 "=S" (*rEBX), 134 "=c" (*rECX), 135 "=d" (*rEDX) 136 : "a" (value), 137 "c" (subleaf)); 138 return false; 139 #elif defined(_MSC_VER) 140 int registers[4]; 141 __cpuidex(registers, value, subleaf); 142 *rEAX = registers[0]; 143 *rEBX = registers[1]; 144 *rECX = registers[2]; 145 *rEDX = registers[3]; 146 return false; 147 #else 148 return true; 149 #endif 150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86) 151 #if defined(__GNUC__) 152 asm ("movl\t%%ebx, %%esi\n\t" 153 "cpuid\n\t" 154 "xchgl\t%%ebx, %%esi\n\t" 155 : "=a" (*rEAX), 156 "=S" (*rEBX), 157 "=c" (*rECX), 158 "=d" (*rEDX) 159 : "a" (value), 160 "c" (subleaf)); 161 return false; 162 #elif defined(_MSC_VER) 163 __asm { 164 mov eax,value 165 mov ecx,subleaf 166 cpuid 167 mov esi,rEAX 168 mov dword ptr [esi],eax 169 mov esi,rEBX 170 mov dword ptr [esi],ebx 171 mov esi,rECX 172 mov dword ptr [esi],ecx 173 mov esi,rEDX 174 mov dword ptr [esi],edx 175 } 176 return false; 177 #else 178 return true; 179 #endif 180 #else 181 return true; 182 #endif 183 } 184 185 static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) { 186 #if defined(__GNUC__) 187 // Check xgetbv; this uses a .byte sequence instead of the instruction 188 // directly because older assemblers do not include support for xgetbv and 189 // there is no easy way to conditionally compile based on the assembler used. 190 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (*rEAX), "=d" (*rEDX) : "c" (0)); 191 return false; 192 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 193 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 194 *rEAX = Result; 195 *rEDX = Result >> 32; 196 return false; 197 #else 198 return true; 199 #endif 200 } 201 202 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, 203 unsigned &Model) { 204 Family = (EAX >> 8) & 0xf; // Bits 8 - 11 205 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 206 if (Family == 6 || Family == 0xf) { 207 if (Family == 0xf) 208 // Examine extended family ID if family ID is F. 209 Family += (EAX >> 20) & 0xff; // Bits 20 - 27 210 // Examine extended model ID if family ID is 6 or F. 211 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 212 } 213 } 214 215 StringRef sys::getHostCPUName() { 216 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 217 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) 218 return "generic"; 219 unsigned Family = 0; 220 unsigned Model = 0; 221 DetectX86FamilyModel(EAX, Family, Model); 222 223 union { 224 unsigned u[3]; 225 char c[12]; 226 } text; 227 228 unsigned MaxLeaf; 229 GetX86CpuIDAndInfo(0, &MaxLeaf, text.u+0, text.u+2, text.u+1); 230 231 bool HasMMX = (EDX >> 23) & 1; 232 bool HasSSE = (EDX >> 25) & 1; 233 bool HasSSE2 = (EDX >> 26) & 1; 234 bool HasSSE3 = (ECX >> 0) & 1; 235 bool HasSSSE3 = (ECX >> 9) & 1; 236 bool HasSSE41 = (ECX >> 19) & 1; 237 bool HasSSE42 = (ECX >> 20) & 1; 238 bool HasMOVBE = (ECX >> 22) & 1; 239 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 240 // indicates that the AVX registers will be saved and restored on context 241 // switch, then we have full AVX support. 242 const unsigned AVXBits = (1 << 27) | (1 << 28); 243 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) && 244 ((EAX & 0x6) == 0x6); 245 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 246 bool HasLeaf7 = MaxLeaf >= 0x7 && 247 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 248 bool HasADX = HasLeaf7 && ((EBX >> 19) & 1); 249 bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20); 250 bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1); 251 252 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 253 bool Em64T = (EDX >> 29) & 0x1; 254 bool HasTBM = (ECX >> 21) & 0x1; 255 256 if (memcmp(text.c, "GenuineIntel", 12) == 0) { 257 switch (Family) { 258 case 3: 259 return "i386"; 260 case 4: 261 switch (Model) { 262 case 0: // Intel486 DX processors 263 case 1: // Intel486 DX processors 264 case 2: // Intel486 SX processors 265 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 266 // IntelDX2 processors 267 case 4: // Intel486 SL processor 268 case 5: // IntelSX2 processors 269 case 7: // Write-Back Enhanced IntelDX2 processors 270 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 271 default: return "i486"; 272 } 273 case 5: 274 switch (Model) { 275 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 276 // Pentium processors (60, 66) 277 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 278 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 279 // 150, 166, 200) 280 case 3: // Pentium OverDrive processors for Intel486 processor-based 281 // systems 282 return "pentium"; 283 284 case 4: // Pentium OverDrive processor with MMX technology for Pentium 285 // processor (75, 90, 100, 120, 133), Pentium processor with 286 // MMX technology (166, 200) 287 return "pentium-mmx"; 288 289 default: return "pentium"; 290 } 291 case 6: 292 switch (Model) { 293 case 1: // Pentium Pro processor 294 return "pentiumpro"; 295 296 case 3: // Intel Pentium II OverDrive processor, Pentium II processor, 297 // model 03 298 case 5: // Pentium II processor, model 05, Pentium II Xeon processor, 299 // model 05, and Intel Celeron processor, model 05 300 case 6: // Celeron processor, model 06 301 return "pentium2"; 302 303 case 7: // Pentium III processor, model 07, and Pentium III Xeon 304 // processor, model 07 305 case 8: // Pentium III processor, model 08, Pentium III Xeon processor, 306 // model 08, and Celeron processor, model 08 307 case 10: // Pentium III Xeon processor, model 0Ah 308 case 11: // Pentium III processor, model 0Bh 309 return "pentium3"; 310 311 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09. 312 case 13: // Intel Pentium M processor, Intel Celeron M processor, model 313 // 0Dh. All processors are manufactured using the 90 nm process. 314 case 21: // Intel EP80579 Integrated Processor and Intel EP80579 315 // Integrated Processor with Intel QuickAssist Technology 316 return "pentium-m"; 317 318 case 14: // Intel Core Duo processor, Intel Core Solo processor, model 319 // 0Eh. All processors are manufactured using the 65 nm process. 320 return "yonah"; 321 322 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 323 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 324 // mobile processor, Intel Core 2 Extreme processor, Intel 325 // Pentium Dual-Core processor, Intel Xeon processor, model 326 // 0Fh. All processors are manufactured using the 65 nm process. 327 case 22: // Intel Celeron processor model 16h. All processors are 328 // manufactured using the 65 nm process 329 return "core2"; 330 331 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model 332 // 17h. All processors are manufactured using the 45 nm process. 333 // 334 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 335 case 29: // Intel Xeon processor MP. All processors are manufactured using 336 // the 45 nm process. 337 return "penryn"; 338 339 case 26: // Intel Core i7 processor and Intel Xeon processor. All 340 // processors are manufactured using the 45 nm process. 341 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 342 // As found in a Summer 2010 model iMac. 343 case 46: // Nehalem EX 344 return "nehalem"; 345 case 37: // Intel Core i7, laptop version. 346 case 44: // Intel Core i7 processor and Intel Xeon processor. All 347 // processors are manufactured using the 32 nm process. 348 case 47: // Westmere EX 349 return "westmere"; 350 351 // SandyBridge: 352 case 42: // Intel Core i7 processor. All processors are manufactured 353 // using the 32 nm process. 354 case 45: 355 return "sandybridge"; 356 357 // Ivy Bridge: 358 case 58: 359 case 62: // Ivy Bridge EP 360 return "ivybridge"; 361 362 // Haswell: 363 case 60: 364 case 63: 365 case 69: 366 case 70: 367 return "haswell"; 368 369 // Broadwell: 370 case 61: 371 case 71: 372 return "broadwell"; 373 374 // Skylake: 375 case 78: 376 case 94: 377 return "skylake"; 378 379 case 28: // Most 45 nm Intel Atom processors 380 case 38: // 45 nm Atom Lincroft 381 case 39: // 32 nm Atom Medfield 382 case 53: // 32 nm Atom Midview 383 case 54: // 32 nm Atom Midview 384 return "bonnell"; 385 386 // Atom Silvermont codes from the Intel software optimization guide. 387 case 55: 388 case 74: 389 case 77: 390 case 90: 391 case 93: 392 return "silvermont"; 393 394 default: // Unknown family 6 CPU, try to guess. 395 if (HasAVX512) 396 return "knl"; 397 if (HasADX) 398 return "broadwell"; 399 if (HasAVX2) 400 return "haswell"; 401 if (HasAVX) 402 return "sandybridge"; 403 if (HasSSE42) 404 return HasMOVBE ? "silvermont" : "nehalem"; 405 if (HasSSE41) 406 return "penryn"; 407 if (HasSSSE3) 408 return HasMOVBE ? "bonnell" : "core2"; 409 if (Em64T) 410 return "x86-64"; 411 if (HasSSE2) 412 return "pentium-m"; 413 if (HasSSE) 414 return "pentium3"; 415 if (HasMMX) 416 return "pentium2"; 417 return "pentiumpro"; 418 } 419 case 15: { 420 switch (Model) { 421 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 422 // model 00h and manufactured using the 0.18 micron process. 423 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 424 // processor MP, and Intel Celeron processor. All processors are 425 // model 01h and manufactured using the 0.18 micron process. 426 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 427 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 428 // processor, and Mobile Intel Celeron processor. All processors 429 // are model 02h and manufactured using the 0.13 micron process. 430 return (Em64T) ? "x86-64" : "pentium4"; 431 432 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 433 // processor. All processors are model 03h and manufactured using 434 // the 90 nm process. 435 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 436 // Pentium D processor, Intel Xeon processor, Intel Xeon 437 // processor MP, Intel Celeron D processor. All processors are 438 // model 04h and manufactured using the 90 nm process. 439 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 440 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 441 // MP, Intel Celeron D processor. All processors are model 06h 442 // and manufactured using the 65 nm process. 443 return (Em64T) ? "nocona" : "prescott"; 444 445 default: 446 return (Em64T) ? "x86-64" : "pentium4"; 447 } 448 } 449 450 default: 451 return "generic"; 452 } 453 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) { 454 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 455 // appears to be no way to generate the wide variety of AMD-specific targets 456 // from the information returned from CPUID. 457 switch (Family) { 458 case 4: 459 return "i486"; 460 case 5: 461 switch (Model) { 462 case 6: 463 case 7: return "k6"; 464 case 8: return "k6-2"; 465 case 9: 466 case 13: return "k6-3"; 467 case 10: return "geode"; 468 default: return "pentium"; 469 } 470 case 6: 471 switch (Model) { 472 case 4: return "athlon-tbird"; 473 case 6: 474 case 7: 475 case 8: return "athlon-mp"; 476 case 10: return "athlon-xp"; 477 default: return "athlon"; 478 } 479 case 15: 480 if (HasSSE3) 481 return "k8-sse3"; 482 switch (Model) { 483 case 1: return "opteron"; 484 case 5: return "athlon-fx"; // also opteron 485 default: return "athlon64"; 486 } 487 case 16: 488 return "amdfam10"; 489 case 20: 490 return "btver1"; 491 case 21: 492 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback. 493 return "btver1"; 494 if (Model >= 0x50) 495 return "bdver4"; // 50h-6Fh: Excavator 496 if (Model >= 0x30) 497 return "bdver3"; // 30h-3Fh: Steamroller 498 if (Model >= 0x10 || HasTBM) 499 return "bdver2"; // 10h-1Fh: Piledriver 500 return "bdver1"; // 00h-0Fh: Bulldozer 501 case 22: 502 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback. 503 return "btver1"; 504 return "btver2"; 505 default: 506 return "generic"; 507 } 508 } 509 return "generic"; 510 } 511 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 512 StringRef sys::getHostCPUName() { 513 host_basic_info_data_t hostInfo; 514 mach_msg_type_number_t infoCount; 515 516 infoCount = HOST_BASIC_INFO_COUNT; 517 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 518 &infoCount); 519 520 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic"; 521 522 switch(hostInfo.cpu_subtype) { 523 case CPU_SUBTYPE_POWERPC_601: return "601"; 524 case CPU_SUBTYPE_POWERPC_602: return "602"; 525 case CPU_SUBTYPE_POWERPC_603: return "603"; 526 case CPU_SUBTYPE_POWERPC_603e: return "603e"; 527 case CPU_SUBTYPE_POWERPC_603ev: return "603ev"; 528 case CPU_SUBTYPE_POWERPC_604: return "604"; 529 case CPU_SUBTYPE_POWERPC_604e: return "604e"; 530 case CPU_SUBTYPE_POWERPC_620: return "620"; 531 case CPU_SUBTYPE_POWERPC_750: return "750"; 532 case CPU_SUBTYPE_POWERPC_7400: return "7400"; 533 case CPU_SUBTYPE_POWERPC_7450: return "7450"; 534 case CPU_SUBTYPE_POWERPC_970: return "970"; 535 default: ; 536 } 537 538 return "generic"; 539 } 540 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 541 StringRef sys::getHostCPUName() { 542 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 543 // and so we must use an operating-system interface to determine the current 544 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 545 const char *generic = "generic"; 546 547 // The cpu line is second (after the 'processor: 0' line), so if this 548 // buffer is too small then something has changed (or is wrong). 549 char buffer[1024]; 550 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 551 if (CPUInfoSize == -1) 552 return generic; 553 554 const char *CPUInfoStart = buffer; 555 const char *CPUInfoEnd = buffer + CPUInfoSize; 556 557 const char *CIP = CPUInfoStart; 558 559 const char *CPUStart = 0; 560 size_t CPULen = 0; 561 562 // We need to find the first line which starts with cpu, spaces, and a colon. 563 // After the colon, there may be some additional spaces and then the cpu type. 564 while (CIP < CPUInfoEnd && CPUStart == 0) { 565 if (CIP < CPUInfoEnd && *CIP == '\n') 566 ++CIP; 567 568 if (CIP < CPUInfoEnd && *CIP == 'c') { 569 ++CIP; 570 if (CIP < CPUInfoEnd && *CIP == 'p') { 571 ++CIP; 572 if (CIP < CPUInfoEnd && *CIP == 'u') { 573 ++CIP; 574 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 575 ++CIP; 576 577 if (CIP < CPUInfoEnd && *CIP == ':') { 578 ++CIP; 579 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 580 ++CIP; 581 582 if (CIP < CPUInfoEnd) { 583 CPUStart = CIP; 584 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 585 *CIP != ',' && *CIP != '\n')) 586 ++CIP; 587 CPULen = CIP - CPUStart; 588 } 589 } 590 } 591 } 592 } 593 594 if (CPUStart == 0) 595 while (CIP < CPUInfoEnd && *CIP != '\n') 596 ++CIP; 597 } 598 599 if (CPUStart == 0) 600 return generic; 601 602 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 603 .Case("604e", "604e") 604 .Case("604", "604") 605 .Case("7400", "7400") 606 .Case("7410", "7400") 607 .Case("7447", "7400") 608 .Case("7455", "7450") 609 .Case("G4", "g4") 610 .Case("POWER4", "970") 611 .Case("PPC970FX", "970") 612 .Case("PPC970MP", "970") 613 .Case("G5", "g5") 614 .Case("POWER5", "g5") 615 .Case("A2", "a2") 616 .Case("POWER6", "pwr6") 617 .Case("POWER7", "pwr7") 618 .Case("POWER8", "pwr8") 619 .Case("POWER8E", "pwr8") 620 .Default(generic); 621 } 622 #elif defined(__linux__) && defined(__arm__) 623 StringRef sys::getHostCPUName() { 624 // The cpuid register on arm is not accessible from user space. On Linux, 625 // it is exposed through the /proc/cpuinfo file. 626 627 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line 628 // in all cases. 629 char buffer[1024]; 630 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 631 if (CPUInfoSize == -1) 632 return "generic"; 633 634 StringRef Str(buffer, CPUInfoSize); 635 636 SmallVector<StringRef, 32> Lines; 637 Str.split(Lines, "\n"); 638 639 // Look for the CPU implementer line. 640 StringRef Implementer; 641 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 642 if (Lines[I].startswith("CPU implementer")) 643 Implementer = Lines[I].substr(15).ltrim("\t :"); 644 645 if (Implementer == "0x41") // ARM Ltd. 646 // Look for the CPU part line. 647 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 648 if (Lines[I].startswith("CPU part")) 649 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 650 // values correspond to the "Part number" in the CP15/c0 register. The 651 // contents are specified in the various processor manuals. 652 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 653 .Case("0x926", "arm926ej-s") 654 .Case("0xb02", "mpcore") 655 .Case("0xb36", "arm1136j-s") 656 .Case("0xb56", "arm1156t2-s") 657 .Case("0xb76", "arm1176jz-s") 658 .Case("0xc08", "cortex-a8") 659 .Case("0xc09", "cortex-a9") 660 .Case("0xc0f", "cortex-a15") 661 .Case("0xc20", "cortex-m0") 662 .Case("0xc23", "cortex-m3") 663 .Case("0xc24", "cortex-m4") 664 .Default("generic"); 665 666 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 667 // Look for the CPU part line. 668 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 669 if (Lines[I].startswith("CPU part")) 670 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 671 // values correspond to the "Part number" in the CP15/c0 register. The 672 // contents are specified in the various processor manuals. 673 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 674 .Case("0x06f", "krait") // APQ8064 675 .Default("generic"); 676 677 return "generic"; 678 } 679 #elif defined(__linux__) && defined(__s390x__) 680 StringRef sys::getHostCPUName() { 681 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 682 683 // The "processor 0:" line comes after a fair amount of other information, 684 // including a cache breakdown, but this should be plenty. 685 char buffer[2048]; 686 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 687 if (CPUInfoSize == -1) 688 return "generic"; 689 690 StringRef Str(buffer, CPUInfoSize); 691 SmallVector<StringRef, 32> Lines; 692 Str.split(Lines, "\n"); 693 694 // Look for the CPU features. 695 SmallVector<StringRef, 32> CPUFeatures; 696 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 697 if (Lines[I].startswith("features")) { 698 size_t Pos = Lines[I].find(":"); 699 if (Pos != StringRef::npos) { 700 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 701 break; 702 } 703 } 704 705 // We need to check for the presence of vector support independently of 706 // the machine type, since we may only use the vector register set when 707 // supported by the kernel (and hypervisor). 708 bool HaveVectorSupport = false; 709 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 710 if (CPUFeatures[I] == "vx") 711 HaveVectorSupport = true; 712 } 713 714 // Now check the processor machine type. 715 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 716 if (Lines[I].startswith("processor ")) { 717 size_t Pos = Lines[I].find("machine = "); 718 if (Pos != StringRef::npos) { 719 Pos += sizeof("machine = ") - 1; 720 unsigned int Id; 721 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 722 if (Id >= 2964 && HaveVectorSupport) 723 return "z13"; 724 if (Id >= 2827) 725 return "zEC12"; 726 if (Id >= 2817) 727 return "z196"; 728 } 729 } 730 break; 731 } 732 } 733 734 return "generic"; 735 } 736 #else 737 StringRef sys::getHostCPUName() { 738 return "generic"; 739 } 740 #endif 741 742 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ 743 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) 744 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 745 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 746 unsigned MaxLevel; 747 union { 748 unsigned u[3]; 749 char c[12]; 750 } text; 751 752 if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) || 753 MaxLevel < 1) 754 return false; 755 756 GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 757 758 Features["cmov"] = (EDX >> 15) & 1; 759 Features["mmx"] = (EDX >> 23) & 1; 760 Features["sse"] = (EDX >> 25) & 1; 761 Features["sse2"] = (EDX >> 26) & 1; 762 Features["sse3"] = (ECX >> 0) & 1; 763 Features["ssse3"] = (ECX >> 9) & 1; 764 Features["sse4.1"] = (ECX >> 19) & 1; 765 Features["sse4.2"] = (ECX >> 20) & 1; 766 767 Features["pclmul"] = (ECX >> 1) & 1; 768 Features["cx16"] = (ECX >> 13) & 1; 769 Features["movbe"] = (ECX >> 22) & 1; 770 Features["popcnt"] = (ECX >> 23) & 1; 771 Features["aes"] = (ECX >> 25) & 1; 772 Features["rdrnd"] = (ECX >> 30) & 1; 773 774 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 775 // indicates that the AVX registers will be saved and restored on context 776 // switch, then we have full AVX support. 777 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 778 !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 779 Features["avx"] = HasAVXSave; 780 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 781 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 782 783 // Only enable XSAVE if OS has enabled support for saving YMM state. 784 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 785 786 // AVX512 requires additional context to be saved by the OS. 787 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 788 789 unsigned MaxExtLevel; 790 GetX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 791 792 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 793 !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 794 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 795 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 796 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 797 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 798 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 799 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 800 801 bool HasLeaf7 = MaxLevel >= 7 && 802 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 803 804 // AVX2 is only supported if we have the OS save support from AVX. 805 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 806 807 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 808 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 809 Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1); 810 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 811 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 812 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 813 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 814 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 815 // Enable protection keys 816 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 817 818 // AVX512 is only supported if the OS supports the context save for it. 819 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 820 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 821 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 822 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 823 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 824 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 825 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 826 827 bool HasLeafD = MaxLevel >= 0xd && 828 !GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 829 830 // Only enable XSAVE if OS has enabled support for saving YMM state. 831 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 832 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 833 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 834 835 return true; 836 } 837 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 838 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 839 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line 840 // in all cases. 841 char buffer[1024]; 842 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer)); 843 if (CPUInfoSize == -1) 844 return false; 845 846 StringRef Str(buffer, CPUInfoSize); 847 848 SmallVector<StringRef, 32> Lines; 849 Str.split(Lines, "\n"); 850 851 SmallVector<StringRef, 32> CPUFeatures; 852 853 // Look for the CPU features. 854 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 855 if (Lines[I].startswith("Features")) { 856 Lines[I].split(CPUFeatures, ' '); 857 break; 858 } 859 860 #if defined(__aarch64__) 861 // Keep track of which crypto features we have seen 862 enum { 863 CAP_AES = 0x1, 864 CAP_PMULL = 0x2, 865 CAP_SHA1 = 0x4, 866 CAP_SHA2 = 0x8 867 }; 868 uint32_t crypto = 0; 869 #endif 870 871 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 872 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 873 #if defined(__aarch64__) 874 .Case("asimd", "neon") 875 .Case("fp", "fp-armv8") 876 .Case("crc32", "crc") 877 #else 878 .Case("half", "fp16") 879 .Case("neon", "neon") 880 .Case("vfpv3", "vfp3") 881 .Case("vfpv3d16", "d16") 882 .Case("vfpv4", "vfp4") 883 .Case("idiva", "hwdiv-arm") 884 .Case("idivt", "hwdiv") 885 #endif 886 .Default(""); 887 888 #if defined(__aarch64__) 889 // We need to check crypto separately since we need all of the crypto 890 // extensions to enable the subtarget feature 891 if (CPUFeatures[I] == "aes") 892 crypto |= CAP_AES; 893 else if (CPUFeatures[I] == "pmull") 894 crypto |= CAP_PMULL; 895 else if (CPUFeatures[I] == "sha1") 896 crypto |= CAP_SHA1; 897 else if (CPUFeatures[I] == "sha2") 898 crypto |= CAP_SHA2; 899 #endif 900 901 if (LLVMFeatureStr != "") 902 Features[LLVMFeatureStr] = true; 903 } 904 905 #if defined(__aarch64__) 906 // If we have all crypto bits we can add the feature 907 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 908 Features["crypto"] = true; 909 #endif 910 911 return true; 912 } 913 #else 914 bool sys::getHostCPUFeatures(StringMap<bool> &Features){ 915 return false; 916 } 917 #endif 918 919 std::string sys::getProcessTriple() { 920 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE)); 921 922 if (sizeof(void *) == 8 && PT.isArch32Bit()) 923 PT = PT.get64BitArchVariant(); 924 if (sizeof(void *) == 4 && PT.isArch64Bit()) 925 PT = PT.get32BitArchVariant(); 926 927 return PT.str(); 928 } 929
