| /external/llvm/include/llvm/MC/ |
| MachineLocation.h | 53 bool isReg() const { return IsRegister; }
|
| MCInst.h | 56 bool isReg() const { return Kind == kRegister; }
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
192 if (Op.isReg()) {
299 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
301 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
304 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
307 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
310 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
313 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS)
[all...] |
| /sdk/find_java2/FindJava2/ |
| FindJava2.cpp | 120 bool isReg = (p == javaPath);
121 if (isReg) {
124 _tprintf(_T("%c [%s] %s\n"), isReg ? '*' : ' ', p.getVersion(), p.mPath);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags;
195 assert(!isReg() && "Register operands can't have target flags");
200 assert(!isReg() && "Register operands can't have target flags");
229 /// isReg - Tests if this is a MO_Register operand.
230 bool isReg() const { return OpKind == MO_Register; }
268 assert(isReg() && "This is not a register operand!");
273 assert(isReg() && "Wrong MachineOperand accessor");
278 assert(isReg() && "Wrong MachineOperand accessor");
283 assert(isReg() && "Wrong MachineOperand accessor");
288 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.h | 325 bool isReg() const { return Kind == K_Reg; }
330 Record *getRegister() const { assert(isReg()); return R; }
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 532 if (MO.isReg()) {
690 if (MCOp1.isImm() && MCOp2.isReg() &&
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 312 bool isReg() const { return Kind == CV_Register; }
316 assert(isReg() && "Wrong CountValue accessor");
320 assert(isReg() && "Wrong CountValue accessor");
329 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
642 if (Op1.isReg()) {
662 if (InitialValue->isReg()) {
669 if (EndValue->isReg()) {
696 if (Start->isReg()) {
702 if (End->isReg()) {
709 if (!Start->isReg() && !Start->isImm()
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 196 bool isReg() const override {
199 bool isReg(RegisterKind RegKind) const {
310 bool isGR32() const { return isReg(GR32Reg); }
311 bool isGRH32() const { return isReg(GRH32Reg); }
313 bool isGR64() const { return isReg(GR64Reg); }
314 bool isGR128() const { return isReg(GR128Reg); }
315 bool isADDR32() const { return isReg(ADDR32Reg); }
316 bool isADDR64() const { return isReg(ADDR64Reg); }
318 bool isFP32() const { return isReg(FP32Reg); }
319 bool isFP64() const { return isReg(FP64Reg);
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 241 bool isReg() const { return Kind == Register; }
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_x86_toIR.c | [all...] |
| guest_amd64_toIR.c | [all...] |
