1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the AArch64 specific subclass of TargetSubtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H 15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H 16 17 #include "AArch64FrameLowering.h" 18 #include "AArch64ISelLowering.h" 19 #include "AArch64InstrInfo.h" 20 #include "AArch64RegisterInfo.h" 21 #include "AArch64SelectionDAGInfo.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/Target/TargetSubtargetInfo.h" 24 #include <string> 25 26 #define GET_SUBTARGETINFO_HEADER 27 #include "AArch64GenSubtargetInfo.inc" 28 29 namespace llvm { 30 class GlobalValue; 31 class StringRef; 32 class Triple; 33 34 class AArch64Subtarget : public AArch64GenSubtargetInfo { 35 protected: 36 enum ARMProcFamilyEnum {Others, CortexA35, CortexA53, CortexA57, Cyclone}; 37 38 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others. 39 ARMProcFamilyEnum ARMProcFamily; 40 41 bool HasV8_1aOps; 42 bool HasV8_2aOps; 43 44 bool HasFPARMv8; 45 bool HasNEON; 46 bool HasCrypto; 47 bool HasCRC; 48 bool HasPerfMon; 49 bool HasFullFP16; 50 bool HasSPE; 51 52 // HasZeroCycleRegMove - Has zero-cycle register mov instructions. 53 bool HasZeroCycleRegMove; 54 55 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions. 56 bool HasZeroCycleZeroing; 57 58 // StrictAlign - Disallow unaligned memory accesses. 59 bool StrictAlign; 60 61 // ReserveX18 - X18 is not available as a general purpose register. 62 bool ReserveX18; 63 64 bool IsLittle; 65 66 /// CPUString - String name of used CPU. 67 std::string CPUString; 68 69 /// TargetTriple - What processor and OS we're targeting. 70 Triple TargetTriple; 71 72 AArch64FrameLowering FrameLowering; 73 AArch64InstrInfo InstrInfo; 74 AArch64SelectionDAGInfo TSInfo; 75 AArch64TargetLowering TLInfo; 76 private: 77 /// initializeSubtargetDependencies - Initializes using CPUString and the 78 /// passed in feature string so that we can use initializer lists for 79 /// subtarget initialization. 80 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS); 81 82 public: 83 /// This constructor initializes the data members to match that 84 /// of the specified triple. 85 AArch64Subtarget(const Triple &TT, const std::string &CPU, 86 const std::string &FS, const TargetMachine &TM, 87 bool LittleEndian); 88 89 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override { 90 return &TSInfo; 91 } 92 const AArch64FrameLowering *getFrameLowering() const override { 93 return &FrameLowering; 94 } 95 const AArch64TargetLowering *getTargetLowering() const override { 96 return &TLInfo; 97 } 98 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; } 99 const AArch64RegisterInfo *getRegisterInfo() const override { 100 return &getInstrInfo()->getRegisterInfo(); 101 } 102 const Triple &getTargetTriple() const { return TargetTriple; } 103 bool enableMachineScheduler() const override { return true; } 104 bool enablePostRAScheduler() const override { 105 return isGeneric() || isCortexA53() || isCortexA57(); 106 } 107 108 bool hasV8_1aOps() const { return HasV8_1aOps; } 109 bool hasV8_2aOps() const { return HasV8_2aOps; } 110 111 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; } 112 113 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } 114 115 bool requiresStrictAlign() const { return StrictAlign; } 116 117 bool isX18Reserved() const { return ReserveX18; } 118 bool hasFPARMv8() const { return HasFPARMv8; } 119 bool hasNEON() const { return HasNEON; } 120 bool hasCrypto() const { return HasCrypto; } 121 bool hasCRC() const { return HasCRC; } 122 /// CPU has TBI (top byte of addresses is ignored during HW address 123 /// translation) and OS enables it. 124 bool supportsAddressTopByteIgnored() const; 125 126 bool hasPerfMon() const { return HasPerfMon; } 127 bool hasFullFP16() const { return HasFullFP16; } 128 bool hasSPE() const { return HasSPE; } 129 130 bool isLittleEndian() const { return IsLittle; } 131 132 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 133 bool isTargetIOS() const { return TargetTriple.isiOS(); } 134 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 135 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 136 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 137 138 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 139 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 140 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 141 142 bool isGeneric() const { return CPUString == "generic"; } 143 bool isCyclone() const { return CPUString == "cyclone"; } 144 bool isCortexA57() const { return CPUString == "cortex-a57"; } 145 bool isCortexA53() const { return CPUString == "cortex-a53"; } 146 147 bool useAA() const override { return isCortexA53(); } 148 149 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 150 /// that still makes it profitable to inline the call. 151 unsigned getMaxInlineSizeThreshold() const { return 64; } 152 153 /// ParseSubtargetFeatures - Parses features string setting specified 154 /// subtarget options. Definition of function is auto generated by tblgen. 155 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 156 157 /// ClassifyGlobalReference - Find the target operand flags that describe 158 /// how a global value should be referenced for the current subtarget. 159 unsigned char ClassifyGlobalReference(const GlobalValue *GV, 160 const TargetMachine &TM) const; 161 162 /// This function returns the name of a function which has an interface 163 /// like the non-standard bzero function, if such a function exists on 164 /// the current subtarget and it is considered prefereable over 165 /// memset with zero passed as the second argument. Otherwise it 166 /// returns null. 167 const char *getBZeroEntry() const; 168 169 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin, 170 MachineInstr *end, 171 unsigned NumRegionInstrs) const override; 172 173 bool enableEarlyIfConversion() const override; 174 175 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override; 176 }; 177 } // End llvm namespace 178 179 #endif 180
