| /external/clang/test/CodeGen/ |
| vector-alignment.c | 48 double __attribute__((vector_size(24))) v9; variable
49 // SSE: @v9 {{.*}}, align 16
50 // AVX: @v9 {{.*}}, align 32
51 // AVX512: @v9 {{.*}}, align 32
|
| ppc64le-aggregates.c | 136 struct v9 { vector int v[9]; }; struct
165 // CHECK: define void @func_v9(%struct.v9* noalias sret %agg.result, %struct.v9* byval align 16 %x)
166 struct v9 func_v9(struct v9 x) { return x; }
223 // CHECK: call void @func_v9(%struct.v9* sret %{{[^ ]+}}, %struct.v9* byval align 16 @global_v9)
224 struct v9 global_v9;
|
| /external/v8/test/mjsunit/ |
| math-min-max.js | 136 var v9 = 9.9;
147 assertEquals(v0, Math.max(v0++, v9++));
148 assertEquals(v9, Math.min(v0++, v9++));
150 assertEquals(v1, Math.min(v1++, v9++)); // int32, double
154 assertEquals(v6, Math.min(v6, v9++)); // tagged, double
162 assertEquals(NaN, Math.min(NaN, v9));
164 assertEquals(NaN, Math.min(v9, NaN));
172 var v9 = {};
173 v9.valueOf = function() { return 6;
[all...] |
| /external/libunwind/tests/ |
| ppc64-test-altivec.c | 39 register vector signed int v9; local
142 v9 =
172 printf ("v9 - ");
173 vec_print (v9);
176 return v9;
|
| /external/boringssl/src/crypto/chacha/ |
| chacha_vec.c | 189 vec v8,v9,v10,v11; local
199 v8 = v4; v9 = v5; v10 = v6;
203 v12 = v8; v13 = v9; v14 = v10;
219 DQROUND_VECTORS(v8,v9,v10,v11)
241 WRITE_XOR(ip, op, 32, v8+s0, v9+s1, v10+s2, v11+s3)
|
| /external/clang/test/SemaCXX/ |
| constant-expression.cpp | 30 v9 = (int)1.5, enumerator in enum:C::E
|
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_ppc_regs.h | 74 #define v9 9 macro
|
| /bionic/libm/upstream-freebsd/lib/msun/ld128/ |
| e_lgammal_r.c | 129 v9 = 1.35364253570403771005922441442688978e-03L, variable
294 y*(v8+y*(v9+y*(v10+y*v11))))))))));
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| sparc-opc.c | 63 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B) macro
64 /* v9 insns supported by leon. */
68 /* v6 insns not supported by v9. */
71 /* v9a instructions which would appear to be aliases to v9's impdep's
86 /* ??? Don't some v8 priviledged insns conflict with v9? */
87 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
88 /* v9 with ultrasparc additions */
90 /* v9 with cheetah additions */
116 /* v9: Move (MOVcc and FMOVcc) condition field. */
117 #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
[all...] |
| /external/libvpx/libvpx/vp9/encoder/x86/ |
| vp9_dct_sse2.c | 927 __m128i v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15; local
[all...] |
| /external/libvpx/libvpx/vpx_dsp/x86/ |
| inv_txfm_sse2.c | 589 __m128i v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15; local
664 v9 = _mm_add_epi32(w9, k__DCT_CONST_ROUNDING);
681 u9 = _mm_srai_epi32(v9, DCT_CONST_BITS);
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/x86/ |
| vp9_idct_intrin_sse2.c | 720 __m128i v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15; local
795 v9 = _mm_add_epi32(w9, k__DCT_CONST_ROUNDING);
812 u9 = _mm_srai_epi32(v9, DCT_CONST_BITS);
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/encoder/x86/ |
| vp9_dct_avx2.c | 824 __m128i v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15; local
[all...] |
| vp9_dct_sse2.c | 925 __m128i v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, v12, v13, v14, v15; local
[all...] |
| /ndk/tests/device/test-stlport_shared-exception/jni/ |
| pr29166.cpp | 18 register int v1=OFF+1,v2=OFF+2,v3=OFF+3,v4=OFF+4,v5=OFF+5,v6=OFF+6,v7=OFF+7,v8=OFF+8,v9=OFF+9,v10=OFF+10; local
49 sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
92 register int v1=OFF+1,v2=OFF+2,v3=OFF+3,v4=OFF+4,v5=OFF+5,v6=OFF+6,v7=OFF+7,v8=OFF+8,v9=OFF+9,v10=OFF+10; local
126 sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
163 sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
|
| /ndk/tests/device/test-stlport_static-exception/jni/ |
| pr29166.cpp | 18 register int v1=OFF+1,v2=OFF+2,v3=OFF+3,v4=OFF+4,v5=OFF+5,v6=OFF+6,v7=OFF+7,v8=OFF+8,v9=OFF+9,v10=OFF+10; local
49 sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
92 register int v1=OFF+1,v2=OFF+2,v3=OFF+3,v4=OFF+4,v5=OFF+5,v6=OFF+6,v7=OFF+7,v8=OFF+8,v9=OFF+9,v10=OFF+10; local
126 sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
163 sum +=v1+v2+v3+v4+v5+v6+v7+v8+v9+v10;
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-sparc.c | 60 In a 32 bit environment, don't allow bumping up to v9 by default.
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
73 /* The currently selected v9 memory model. Currently only used for
110 /* Symbols for global registers on v9. */
116 /* V9 and 86x have big and little endian data, but instructions are always big
223 v8plusa, v9, v9a, v9b, v9_64};
260 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
261 { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 }
222 v8plusa, v9, v9a, v9b, v9_64}; enumerator in enum:sparc_arch_types
[all...] |
