1 /* CPU data for xc16x. 2 3 THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5 Copyright (C) 1996-2014 Free Software Foundation, Inc. 6 7 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23 */ 24 25 #include "sysdep.h" 26 #include <stdio.h> 27 #include <stdarg.h> 28 #include "ansidecl.h" 29 #include "bfd.h" 30 #include "symcat.h" 31 #include "xc16x-desc.h" 32 #include "xc16x-opc.h" 33 #include "opintl.h" 34 #include "libiberty.h" 35 #include "xregex.h" 36 37 /* Attributes. */ 38 39 static const CGEN_ATTR_ENTRY bool_attr[] = 40 { 41 { "#f", 0 }, 42 { "#t", 1 }, 43 { 0, 0 } 44 }; 45 46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 47 { 48 { "base", MACH_BASE }, 49 { "xc16x", MACH_XC16X }, 50 { "max", MACH_MAX }, 51 { 0, 0 } 52 }; 53 54 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 55 { 56 { "xc16x", ISA_XC16X }, 57 { "max", ISA_MAX }, 58 { 0, 0 } 59 }; 60 61 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED = 62 { 63 { "NONE", PIPE_NONE }, 64 { "OS", PIPE_OS }, 65 { 0, 0 } 66 }; 67 68 const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] = 69 { 70 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 71 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 72 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 73 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 74 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 75 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 76 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 77 { "RELOC", &bool_attr[0], &bool_attr[0] }, 78 { 0, 0, 0 } 79 }; 80 81 const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] = 82 { 83 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 84 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 85 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 86 { "PC", &bool_attr[0], &bool_attr[0] }, 87 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 88 { 0, 0, 0 } 89 }; 90 91 const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] = 92 { 93 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 94 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 95 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 96 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 97 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 98 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 99 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 100 { "RELAX", &bool_attr[0], &bool_attr[0] }, 101 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 102 { "RELOC", &bool_attr[0], &bool_attr[0] }, 103 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, 104 { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] }, 105 { "POF-PREFIX", &bool_attr[0], &bool_attr[0] }, 106 { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] }, 107 { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] }, 108 { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] }, 109 { 0, 0, 0 } 110 }; 111 112 const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] = 113 { 114 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 115 { "PIPE", & PIPE_attr[0], & PIPE_attr[0] }, 116 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 117 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 118 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 119 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 120 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 121 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 122 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 123 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 124 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 125 { "PBB", &bool_attr[0], &bool_attr[0] }, 126 { 0, 0, 0 } 127 }; 128 129 /* Instruction set variants. */ 130 131 static const CGEN_ISA xc16x_cgen_isa_table[] = { 132 { "xc16x", 16, 32, 16, 32 }, 133 { 0, 0, 0, 0, 0 } 134 }; 135 136 /* Machine variants. */ 137 138 static const CGEN_MACH xc16x_cgen_mach_table[] = { 139 { "xc16x", "xc16x", MACH_XC16X, 32 }, 140 { 0, 0, 0, 0 } 141 }; 142 143 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] = 144 { 145 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 146 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 147 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 148 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 149 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 150 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 151 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 152 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 153 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 154 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 155 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 156 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 157 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 158 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 159 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 160 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 } 161 }; 162 163 CGEN_KEYWORD xc16x_cgen_opval_gr_names = 164 { 165 & xc16x_cgen_opval_gr_names_entries[0], 166 16, 167 0, 0, 0, 0, "" 168 }; 169 170 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] = 171 { 172 { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 }, 173 { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 }, 174 { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 }, 175 { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 }, 176 { "1", 0, {0, {{{0, 0}}}}, 0, 0 }, 177 { "2", 1, {0, {{{0, 0}}}}, 0, 0 }, 178 { "3", 2, {0, {{{0, 0}}}}, 0, 0 }, 179 { "4", 3, {0, {{{0, 0}}}}, 0, 0 } 180 }; 181 182 CGEN_KEYWORD xc16x_cgen_opval_ext_names = 183 { 184 & xc16x_cgen_opval_ext_names_entries[0], 185 8, 186 0, 0, 0, 0, "" 187 }; 188 189 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] = 190 { 191 { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 }, 192 { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 }, 193 { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 }, 194 { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 }, 195 { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 }, 196 { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 }, 197 { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 }, 198 { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 }, 199 { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 }, 200 { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 }, 201 { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 }, 202 { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 }, 203 { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 }, 204 { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 }, 205 { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 }, 206 { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 }, 207 { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 } 208 }; 209 210 CGEN_KEYWORD xc16x_cgen_opval_psw_names = 211 { 212 & xc16x_cgen_opval_psw_names_entries[0], 213 17, 214 0, 0, 0, 0, "" 215 }; 216 217 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] = 218 { 219 { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 }, 220 { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 }, 221 { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 }, 222 { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 }, 223 { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 }, 224 { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 }, 225 { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 }, 226 { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 }, 227 { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 }, 228 { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 }, 229 { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 }, 230 { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 }, 231 { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 }, 232 { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 }, 233 { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 }, 234 { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 } 235 }; 236 237 CGEN_KEYWORD xc16x_cgen_opval_grb_names = 238 { 239 & xc16x_cgen_opval_grb_names_entries[0], 240 16, 241 0, 0, 0, 0, "" 242 }; 243 244 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] = 245 { 246 { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 }, 247 { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 }, 248 { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 }, 249 { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 }, 250 { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 }, 251 { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 }, 252 { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 }, 253 { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 }, 254 { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 }, 255 { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 }, 256 { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 }, 257 { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 }, 258 { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 }, 259 { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 }, 260 { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 }, 261 { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 }, 262 { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 }, 263 { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 }, 264 { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 }, 265 { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 } 266 }; 267 268 CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names = 269 { 270 & xc16x_cgen_opval_conditioncode_names_entries[0], 271 20, 272 0, 0, 0, 0, "" 273 }; 274 275 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] = 276 { 277 { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 }, 278 { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 }, 279 { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 }, 280 { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 }, 281 { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 }, 282 { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 }, 283 { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 }, 284 { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 }, 285 { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 }, 286 { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 }, 287 { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 }, 288 { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 }, 289 { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 }, 290 { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 }, 291 { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 }, 292 { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 }, 293 { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 }, 294 { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 }, 295 { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 }, 296 { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 }, 297 { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 }, 298 { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 }, 299 { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 }, 300 { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 } 301 }; 302 303 CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names = 304 { 305 & xc16x_cgen_opval_extconditioncode_names_entries[0], 306 24, 307 0, 0, 0, 0, "" 308 }; 309 310 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] = 311 { 312 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, 313 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, 314 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, 315 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, 316 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, 317 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, 318 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, 319 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, 320 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, 321 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, 322 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, 323 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, 324 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, 325 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, 326 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, 327 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, 328 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, 329 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, 330 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, 331 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, 332 { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 }, 333 { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 }, 334 { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 }, 335 { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 }, 336 { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 }, 337 { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 }, 338 { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 }, 339 { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 }, 340 { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 }, 341 { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 }, 342 { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 }, 343 { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 }, 344 { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 }, 345 { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 }, 346 { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 }, 347 { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 } 348 }; 349 350 CGEN_KEYWORD xc16x_cgen_opval_grb8_names = 351 { 352 & xc16x_cgen_opval_grb8_names_entries[0], 353 36, 354 0, 0, 0, 0, "" 355 }; 356 357 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] = 358 { 359 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, 360 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, 361 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, 362 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, 363 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, 364 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, 365 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, 366 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, 367 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, 368 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, 369 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, 370 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, 371 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, 372 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, 373 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, 374 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, 375 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, 376 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, 377 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, 378 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, 379 { "r0", 240, {0, {{{0, 0}}}}, 0, 0 }, 380 { "r1", 241, {0, {{{0, 0}}}}, 0, 0 }, 381 { "r2", 242, {0, {{{0, 0}}}}, 0, 0 }, 382 { "r3", 243, {0, {{{0, 0}}}}, 0, 0 }, 383 { "r4", 244, {0, {{{0, 0}}}}, 0, 0 }, 384 { "r5", 245, {0, {{{0, 0}}}}, 0, 0 }, 385 { "r6", 246, {0, {{{0, 0}}}}, 0, 0 }, 386 { "r7", 247, {0, {{{0, 0}}}}, 0, 0 }, 387 { "r8", 248, {0, {{{0, 0}}}}, 0, 0 }, 388 { "r9", 249, {0, {{{0, 0}}}}, 0, 0 }, 389 { "r10", 250, {0, {{{0, 0}}}}, 0, 0 }, 390 { "r11", 251, {0, {{{0, 0}}}}, 0, 0 }, 391 { "r12", 252, {0, {{{0, 0}}}}, 0, 0 }, 392 { "r13", 253, {0, {{{0, 0}}}}, 0, 0 }, 393 { "r14", 254, {0, {{{0, 0}}}}, 0, 0 }, 394 { "r15", 255, {0, {{{0, 0}}}}, 0, 0 } 395 }; 396 397 CGEN_KEYWORD xc16x_cgen_opval_r8_names = 398 { 399 & xc16x_cgen_opval_r8_names_entries[0], 400 36, 401 0, 0, 0, 0, "" 402 }; 403 404 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] = 405 { 406 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, 407 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, 408 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, 409 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, 410 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, 411 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, 412 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, 413 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, 414 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, 415 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, 416 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, 417 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, 418 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, 419 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, 420 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, 421 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, 422 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, 423 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, 424 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, 425 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, 426 { "r0", 240, {0, {{{0, 0}}}}, 0, 0 }, 427 { "r1", 241, {0, {{{0, 0}}}}, 0, 0 }, 428 { "r2", 242, {0, {{{0, 0}}}}, 0, 0 }, 429 { "r3", 243, {0, {{{0, 0}}}}, 0, 0 }, 430 { "r4", 244, {0, {{{0, 0}}}}, 0, 0 }, 431 { "r5", 245, {0, {{{0, 0}}}}, 0, 0 }, 432 { "r6", 246, {0, {{{0, 0}}}}, 0, 0 }, 433 { "r7", 247, {0, {{{0, 0}}}}, 0, 0 }, 434 { "r8", 248, {0, {{{0, 0}}}}, 0, 0 }, 435 { "r9", 249, {0, {{{0, 0}}}}, 0, 0 }, 436 { "r10", 250, {0, {{{0, 0}}}}, 0, 0 }, 437 { "r11", 251, {0, {{{0, 0}}}}, 0, 0 }, 438 { "r12", 252, {0, {{{0, 0}}}}, 0, 0 }, 439 { "r13", 253, {0, {{{0, 0}}}}, 0, 0 }, 440 { "r14", 254, {0, {{{0, 0}}}}, 0, 0 }, 441 { "r15", 255, {0, {{{0, 0}}}}, 0, 0 } 442 }; 443 444 CGEN_KEYWORD xc16x_cgen_opval_regmem8_names = 445 { 446 & xc16x_cgen_opval_regmem8_names_entries[0], 447 36, 448 0, 0, 0, 0, "" 449 }; 450 451 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] = 452 { 453 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 454 { "r1", 17, {0, {{{0, 0}}}}, 0, 0 }, 455 { "r2", 34, {0, {{{0, 0}}}}, 0, 0 }, 456 { "r3", 51, {0, {{{0, 0}}}}, 0, 0 }, 457 { "r4", 68, {0, {{{0, 0}}}}, 0, 0 }, 458 { "r5", 85, {0, {{{0, 0}}}}, 0, 0 }, 459 { "r6", 102, {0, {{{0, 0}}}}, 0, 0 }, 460 { "r7", 119, {0, {{{0, 0}}}}, 0, 0 }, 461 { "r8", 136, {0, {{{0, 0}}}}, 0, 0 }, 462 { "r9", 153, {0, {{{0, 0}}}}, 0, 0 }, 463 { "r10", 170, {0, {{{0, 0}}}}, 0, 0 }, 464 { "r11", 187, {0, {{{0, 0}}}}, 0, 0 }, 465 { "r12", 204, {0, {{{0, 0}}}}, 0, 0 }, 466 { "r13", 221, {0, {{{0, 0}}}}, 0, 0 }, 467 { "r14", 238, {0, {{{0, 0}}}}, 0, 0 }, 468 { "r15", 255, {0, {{{0, 0}}}}, 0, 0 } 469 }; 470 471 CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names = 472 { 473 & xc16x_cgen_opval_regdiv8_names_entries[0], 474 16, 475 0, 0, 0, 0, "" 476 }; 477 478 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] = 479 { 480 { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 }, 481 { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 }, 482 { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 }, 483 { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 }, 484 { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 }, 485 { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 }, 486 { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 }, 487 { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 }, 488 { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 }, 489 { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 }, 490 { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 }, 491 { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 }, 492 { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 }, 493 { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 }, 494 { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 }, 495 { "1", 1, {0, {{{0, 0}}}}, 0, 0 }, 496 { "2", 2, {0, {{{0, 0}}}}, 0, 0 }, 497 { "3", 3, {0, {{{0, 0}}}}, 0, 0 }, 498 { "4", 4, {0, {{{0, 0}}}}, 0, 0 }, 499 { "5", 5, {0, {{{0, 0}}}}, 0, 0 }, 500 { "6", 6, {0, {{{0, 0}}}}, 0, 0 }, 501 { "7", 7, {0, {{{0, 0}}}}, 0, 0 }, 502 { "8", 8, {0, {{{0, 0}}}}, 0, 0 }, 503 { "9", 9, {0, {{{0, 0}}}}, 0, 0 }, 504 { "10", 10, {0, {{{0, 0}}}}, 0, 0 }, 505 { "11", 11, {0, {{{0, 0}}}}, 0, 0 }, 506 { "12", 12, {0, {{{0, 0}}}}, 0, 0 }, 507 { "13", 13, {0, {{{0, 0}}}}, 0, 0 }, 508 { "14", 14, {0, {{{0, 0}}}}, 0, 0 }, 509 { "15", 15, {0, {{{0, 0}}}}, 0, 0 } 510 }; 511 512 CGEN_KEYWORD xc16x_cgen_opval_reg0_name = 513 { 514 & xc16x_cgen_opval_reg0_name_entries[0], 515 30, 516 0, 0, 0, 0, "" 517 }; 518 519 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] = 520 { 521 { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 }, 522 { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 }, 523 { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 }, 524 { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 }, 525 { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 }, 526 { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 }, 527 { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 }, 528 { "1", 1, {0, {{{0, 0}}}}, 0, 0 }, 529 { "2", 2, {0, {{{0, 0}}}}, 0, 0 }, 530 { "3", 3, {0, {{{0, 0}}}}, 0, 0 }, 531 { "4", 4, {0, {{{0, 0}}}}, 0, 0 }, 532 { "5", 5, {0, {{{0, 0}}}}, 0, 0 }, 533 { "6", 6, {0, {{{0, 0}}}}, 0, 0 }, 534 { "7", 7, {0, {{{0, 0}}}}, 0, 0 } 535 }; 536 537 CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 = 538 { 539 & xc16x_cgen_opval_reg0_name1_entries[0], 540 14, 541 0, 0, 0, 0, "" 542 }; 543 544 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] = 545 { 546 { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 }, 547 { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 }, 548 { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 }, 549 { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 }, 550 { "psw", 136, {0, {{{0, 0}}}}, 0, 0 }, 551 { "cp", 8, {0, {{{0, 0}}}}, 0, 0 }, 552 { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 }, 553 { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 }, 554 { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 }, 555 { "sp", 9, {0, {{{0, 0}}}}, 0, 0 }, 556 { "csp", 4, {0, {{{0, 0}}}}, 0, 0 }, 557 { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 }, 558 { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 }, 559 { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 }, 560 { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 }, 561 { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 }, 562 { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 }, 563 { "ones", 143, {0, {{{0, 0}}}}, 0, 0 }, 564 { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 }, 565 { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 }, 566 { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 }, 567 { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 }, 568 { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 }, 569 { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 }, 570 { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 }, 571 { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 }, 572 { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 }, 573 { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 }, 574 { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 }, 575 { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 }, 576 { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 }, 577 { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 }, 578 { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 }, 579 { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 }, 580 { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 }, 581 { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 } 582 }; 583 584 CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names = 585 { 586 & xc16x_cgen_opval_regbmem8_names_entries[0], 587 36, 588 0, 0, 0, 0, "" 589 }; 590 591 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] = 592 { 593 { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 }, 594 { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 }, 595 { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 }, 596 { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 }, 597 { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 }, 598 { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 }, 599 { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 }, 600 { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 }, 601 { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 }, 602 { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 }, 603 { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 }, 604 { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 }, 605 { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 }, 606 { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 }, 607 { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 }, 608 { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 }, 609 { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 }, 610 { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 }, 611 { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 }, 612 { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 } 613 }; 614 615 CGEN_KEYWORD xc16x_cgen_opval_memgr8_names = 616 { 617 & xc16x_cgen_opval_memgr8_names_entries[0], 618 20, 619 0, 0, 0, 0, "" 620 }; 621 622 623 /* The hardware table. */ 624 625 #define A(a) (1 << CGEN_HW_##a) 626 627 const CGEN_HW_ENTRY xc16x_cgen_hw_table[] = 628 { 629 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 630 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 631 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 632 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 633 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 634 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 635 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 636 { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 637 { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 638 { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 639 { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 640 { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 641 { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 642 { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 643 { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 644 { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 645 { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 646 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 647 { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 648 { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } }, 649 { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 650 { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 651 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 652 { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 653 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 654 }; 655 656 #undef A 657 658 659 /* The instruction field table. */ 660 661 #define A(a) (1 << CGEN_IFLD_##a) 662 663 const CGEN_IFLD xc16x_cgen_ifld_table[] = 664 { 665 { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 666 { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 667 { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 668 { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 669 { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 670 { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 671 { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 672 { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 673 { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 674 { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 675 { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 676 { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 677 { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 678 { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 679 { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 680 { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 681 { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 682 { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 683 { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 684 { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 685 { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 686 { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 687 { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 688 { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 689 { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 690 { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 691 { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 692 { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 693 { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 694 { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 695 { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 696 { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 697 { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 698 { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 699 { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 700 { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 701 { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 702 { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 703 { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 704 { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 705 { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 706 { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 707 { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 708 { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 709 { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 710 { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 711 { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 712 { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 713 { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 714 { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 715 { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 716 { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 717 { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 718 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 719 }; 720 721 #undef A 722 723 724 725 /* multi ifield declarations */ 726 727 728 729 /* multi ifield definitions */ 730 731 732 /* The operand table. */ 733 734 #define A(a) (1 << CGEN_OPERAND_##a) 735 #define OPERAND(op) XC16X_OPERAND_##op 736 737 const CGEN_OPERAND xc16x_cgen_operand_table[] = 738 { 739 /* pc: program counter */ 740 { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0, 741 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } }, 742 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 743 /* sr: source register */ 744 { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4, 745 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 746 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 747 /* dr: destination register */ 748 { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4, 749 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 750 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 751 /* dri: destination register */ 752 { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4, 753 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } }, 754 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 755 /* srb: source register */ 756 { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4, 757 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 758 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 759 /* drb: destination register */ 760 { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4, 761 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 762 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 763 /* sr2: 2 bit source register */ 764 { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2, 765 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } }, 766 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 767 /* src1: source register 1 */ 768 { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4, 769 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 770 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 771 /* src2: source register 2 */ 772 { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4, 773 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 774 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 775 /* srdiv: source register 2 */ 776 { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8, 777 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 778 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 779 /* RegNam: PSW bits */ 780 { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8, 781 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 782 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 783 /* uimm2: 2 bit unsigned number */ 784 { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2, 785 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } }, 786 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 787 /* uimm3: 3 bit unsigned number */ 788 { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3, 789 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } }, 790 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 791 /* uimm4: 4 bit unsigned number */ 792 { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4, 793 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } }, 794 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 795 /* uimm7: 7 bit trap number */ 796 { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7, 797 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } }, 798 { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 799 /* uimm8: 8 bit unsigned immediate */ 800 { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8, 801 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } }, 802 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 803 /* uimm16: 16 bit unsigned immediate */ 804 { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16, 805 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } }, 806 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 807 /* upof16: 16 bit unsigned immediate */ 808 { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16, 809 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } }, 810 { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 811 /* reg8: 8 bit word register number */ 812 { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8, 813 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 814 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 815 /* regmem8: 8 bit word register number */ 816 { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8, 817 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } }, 818 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 819 /* regbmem8: 8 bit byte register number */ 820 { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8, 821 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } }, 822 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 823 /* regoff8: 8 bit word register number */ 824 { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8, 825 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } }, 826 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 827 /* reghi8: 8 bit word register number */ 828 { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8, 829 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } }, 830 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 831 /* regb8: 8 bit byte register number */ 832 { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8, 833 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } }, 834 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 835 /* genreg: 8 bit word register number */ 836 { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8, 837 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } }, 838 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 839 /* seg: 8 bit segment number */ 840 { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8, 841 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } }, 842 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 843 /* seghi8: 8 bit hi segment number */ 844 { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8, 845 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } }, 846 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 847 /* caddr: 16 bit address offset */ 848 { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16, 849 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 850 { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 851 /* rel: 8 bit signed relative offset */ 852 { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8, 853 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } }, 854 { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 855 /* relhi: hi 8 bit signed relative offset */ 856 { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8, 857 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } }, 858 { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 859 /* condbit: condition bit */ 860 { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0, 861 { 0, { (const PTR) 0 } }, 862 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 863 /* bit1: gap of 1 bit */ 864 { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1, 865 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } }, 866 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 867 /* bit2: gap of 2 bits */ 868 { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2, 869 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } }, 870 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 871 /* bit4: gap of 4 bits */ 872 { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4, 873 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } }, 874 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 875 /* lbit4: gap of 4 bits */ 876 { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4, 877 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } }, 878 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 879 /* lbit2: gap of 2 bits */ 880 { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2, 881 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } }, 882 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 883 /* bit8: gap of 8 bits */ 884 { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8, 885 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } }, 886 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 887 /* u4: gap of 4 bits */ 888 { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4, 889 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } }, 890 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 891 /* bitone: field of 1 bit */ 892 { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1, 893 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } }, 894 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 895 /* bit01: field of 1 bit */ 896 { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1, 897 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } }, 898 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 899 /* cond: condition code */ 900 { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4, 901 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } }, 902 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 903 /* icond: indirect condition code */ 904 { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4, 905 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } }, 906 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 907 /* extcond: extended condition code */ 908 { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5, 909 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } }, 910 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 911 /* memory: 16 bit memory */ 912 { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16, 913 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } }, 914 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 915 /* memgr8: 16 bit memory */ 916 { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16, 917 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } }, 918 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 919 /* cbit: carry bit */ 920 { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0, 921 { 0, { (const PTR) 0 } }, 922 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 923 /* qbit: bit addr */ 924 { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4, 925 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } }, 926 { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 927 /* qlobit: bit addr */ 928 { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4, 929 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } }, 930 { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 931 /* qhibit: bit addr */ 932 { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4, 933 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } }, 934 { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 935 /* mask8: 8 bit mask */ 936 { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8, 937 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } }, 938 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 939 /* masklo8: 8 bit mask */ 940 { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8, 941 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } }, 942 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 943 /* pagenum: 10 bit page number */ 944 { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10, 945 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } }, 946 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 947 /* data8: 8 bit data */ 948 { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8, 949 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } }, 950 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 951 /* datahi8: 8 bit data */ 952 { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8, 953 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } }, 954 { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 955 /* sgtdisbit: segmentation enable bit */ 956 { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0, 957 { 0, { (const PTR) 0 } }, 958 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 959 /* upag16: 16 bit unsigned immediate */ 960 { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16, 961 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } }, 962 { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 963 /* useg8: 8 bit segment */ 964 { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8, 965 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } }, 966 { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } } }, 967 /* useg16: 16 bit address offset */ 968 { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16, 969 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 970 { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 971 /* usof16: 16 bit address offset */ 972 { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16, 973 { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 974 { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 975 /* hash: # prefix */ 976 { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0, 977 { 0, { (const PTR) 0 } }, 978 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 979 /* dot: . prefix */ 980 { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0, 981 { 0, { (const PTR) 0 } }, 982 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 983 /* pof: pof: prefix */ 984 { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0, 985 { 0, { (const PTR) 0 } }, 986 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 987 /* pag: pag: prefix */ 988 { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0, 989 { 0, { (const PTR) 0 } }, 990 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 991 /* sof: sof: prefix */ 992 { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0, 993 { 0, { (const PTR) 0 } }, 994 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 995 /* segm: seg: prefix */ 996 { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0, 997 { 0, { (const PTR) 0 } }, 998 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 999 /* sentinel */ 1000 { 0, 0, 0, 0, 0, 1001 { 0, { (const PTR) 0 } }, 1002 { 0, { { { (1<<MACH_BASE), 0 } } } } } 1003 }; 1004 1005 #undef A 1006 1007 1008 /* The instruction table. */ 1009 1010 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 1011 #define A(a) (1 << CGEN_INSN_##a) 1012 1013 static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] = 1014 { 1015 /* Special null first entry. 1016 A `num' value of zero is thus invalid. 1017 Also, the special `invalid' insn resides here. */ 1018 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } }, 1019 /* add $reg8,$pof$upof16 */ 1020 { 1021 XC16X_INSN_ADDRPOF, "addrpof", "add", 32, 1022 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1023 }, 1024 /* sub $reg8,$pof$upof16 */ 1025 { 1026 XC16X_INSN_SUBRPOF, "subrpof", "sub", 32, 1027 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1028 }, 1029 /* addb $regb8,$pof$upof16 */ 1030 { 1031 XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32, 1032 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1033 }, 1034 /* subb $regb8,$pof$upof16 */ 1035 { 1036 XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32, 1037 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1038 }, 1039 /* add $reg8,$pag$upag16 */ 1040 { 1041 XC16X_INSN_ADDRPAG, "addrpag", "add", 32, 1042 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1043 }, 1044 /* sub $reg8,$pag$upag16 */ 1045 { 1046 XC16X_INSN_SUBRPAG, "subrpag", "sub", 32, 1047 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1048 }, 1049 /* addb $regb8,$pag$upag16 */ 1050 { 1051 XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32, 1052 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1053 }, 1054 /* subb $regb8,$pag$upag16 */ 1055 { 1056 XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32, 1057 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1058 }, 1059 /* addc $reg8,$pof$upof16 */ 1060 { 1061 XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32, 1062 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1063 }, 1064 /* subc $reg8,$pof$upof16 */ 1065 { 1066 XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32, 1067 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1068 }, 1069 /* addcb $regb8,$pof$upof16 */ 1070 { 1071 XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32, 1072 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1073 }, 1074 /* subcb $regb8,$pof$upof16 */ 1075 { 1076 XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32, 1077 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1078 }, 1079 /* addc $reg8,$pag$upag16 */ 1080 { 1081 XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32, 1082 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1083 }, 1084 /* subc $reg8,$pag$upag16 */ 1085 { 1086 XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32, 1087 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1088 }, 1089 /* addcb $regb8,$pag$upag16 */ 1090 { 1091 XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32, 1092 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1093 }, 1094 /* subcb $regb8,$pag$upag16 */ 1095 { 1096 XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32, 1097 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1098 }, 1099 /* add $pof$upof16,$reg8 */ 1100 { 1101 XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32, 1102 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1103 }, 1104 /* sub $pof$upof16,$reg8 */ 1105 { 1106 XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32, 1107 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1108 }, 1109 /* addb $pof$upof16,$regb8 */ 1110 { 1111 XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32, 1112 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1113 }, 1114 /* subb $pof$upof16,$regb8 */ 1115 { 1116 XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32, 1117 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1118 }, 1119 /* addc $pof$upof16,$reg8 */ 1120 { 1121 XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32, 1122 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1123 }, 1124 /* subc $pof$upof16,$reg8 */ 1125 { 1126 XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32, 1127 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1128 }, 1129 /* addcb $pof$upof16,$regb8 */ 1130 { 1131 XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32, 1132 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1133 }, 1134 /* subcb $pof$upof16,$regb8 */ 1135 { 1136 XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32, 1137 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1138 }, 1139 /* add $reg8,$hash$pof$uimm16 */ 1140 { 1141 XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32, 1142 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1143 }, 1144 /* sub $reg8,$hash$pof$uimm16 */ 1145 { 1146 XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32, 1147 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1148 }, 1149 /* add $reg8,$hash$pag$uimm16 */ 1150 { 1151 XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32, 1152 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1153 }, 1154 /* sub $reg8,$hash$pag$uimm16 */ 1155 { 1156 XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32, 1157 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1158 }, 1159 /* add $dr,$hash$pof$uimm3 */ 1160 { 1161 XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16, 1162 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1163 }, 1164 /* sub $dr,$hash$pof$uimm3 */ 1165 { 1166 XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16, 1167 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1168 }, 1169 /* addb $drb,$hash$pag$uimm3 */ 1170 { 1171 XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16, 1172 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1173 }, 1174 /* subb $drb,$hash$pag$uimm3 */ 1175 { 1176 XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16, 1177 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1178 }, 1179 /* add $dr,$hash$pag$uimm3 */ 1180 { 1181 XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16, 1182 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1183 }, 1184 /* sub $dr,$hash$pag$uimm3 */ 1185 { 1186 XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16, 1187 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1188 }, 1189 /* addb $drb,$hash$pof$uimm3 */ 1190 { 1191 XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16, 1192 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1193 }, 1194 /* subb $drb,$hash$pof$uimm3 */ 1195 { 1196 XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16, 1197 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1198 }, 1199 /* addb $regb8,$hash$pof$uimm8 */ 1200 { 1201 XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32, 1202 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1203 }, 1204 /* subb $regb8,$hash$pof$uimm8 */ 1205 { 1206 XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32, 1207 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1208 }, 1209 /* addb $regb8,$hash$pag$uimm8 */ 1210 { 1211 XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32, 1212 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1213 }, 1214 /* subb $regb8,$hash$pag$uimm8 */ 1215 { 1216 XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32, 1217 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1218 }, 1219 /* addc $reg8,$hash$pof$uimm16 */ 1220 { 1221 XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32, 1222 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1223 }, 1224 /* subc $reg8,$hash$pof$uimm16 */ 1225 { 1226 XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32, 1227 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1228 }, 1229 /* addc $reg8,$hash$pag$uimm16 */ 1230 { 1231 XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32, 1232 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1233 }, 1234 /* subc $reg8,$hash$pag$uimm16 */ 1235 { 1236 XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32, 1237 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1238 }, 1239 /* addc $dr,$hash$pof$uimm3 */ 1240 { 1241 XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16, 1242 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1243 }, 1244 /* subc $dr,$hash$pof$uimm3 */ 1245 { 1246 XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16, 1247 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1248 }, 1249 /* addcb $drb,$hash$pag$uimm3 */ 1250 { 1251 XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16, 1252 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1253 }, 1254 /* subcb $drb,$hash$pag$uimm3 */ 1255 { 1256 XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16, 1257 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1258 }, 1259 /* addc $dr,$hash$pag$uimm3 */ 1260 { 1261 XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16, 1262 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1263 }, 1264 /* subc $dr,$hash$pag$uimm3 */ 1265 { 1266 XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16, 1267 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1268 }, 1269 /* addcb $drb,$hash$pof$uimm3 */ 1270 { 1271 XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16, 1272 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1273 }, 1274 /* subcb $drb,$hash$pof$uimm3 */ 1275 { 1276 XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16, 1277 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1278 }, 1279 /* addcb $regb8,$hash$pof$uimm8 */ 1280 { 1281 XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32, 1282 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1283 }, 1284 /* subcb $regb8,$hash$pof$uimm8 */ 1285 { 1286 XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32, 1287 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1288 }, 1289 /* addcb $regb8,$hash$pag$uimm8 */ 1290 { 1291 XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32, 1292 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1293 }, 1294 /* subcb $regb8,$hash$pag$uimm8 */ 1295 { 1296 XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32, 1297 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1298 }, 1299 /* add $dr,$hash$uimm3 */ 1300 { 1301 XC16X_INSN_ADDRI, "addri", "add", 16, 1302 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1303 }, 1304 /* sub $dr,$hash$uimm3 */ 1305 { 1306 XC16X_INSN_SUBRI, "subri", "sub", 16, 1307 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1308 }, 1309 /* addb $drb,$hash$uimm3 */ 1310 { 1311 XC16X_INSN_ADDBRI, "addbri", "addb", 16, 1312 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1313 }, 1314 /* subb $drb,$hash$uimm3 */ 1315 { 1316 XC16X_INSN_SUBBRI, "subbri", "subb", 16, 1317 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1318 }, 1319 /* add $reg8,$hash$uimm16 */ 1320 { 1321 XC16X_INSN_ADDRIM, "addrim", "add", 32, 1322 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1323 }, 1324 /* sub $reg8,$hash$uimm16 */ 1325 { 1326 XC16X_INSN_SUBRIM, "subrim", "sub", 32, 1327 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1328 }, 1329 /* addb $regb8,$hash$uimm8 */ 1330 { 1331 XC16X_INSN_ADDBRIM, "addbrim", "addb", 32, 1332 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1333 }, 1334 /* subb $regb8,$hash$uimm8 */ 1335 { 1336 XC16X_INSN_SUBBRIM, "subbrim", "subb", 32, 1337 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1338 }, 1339 /* addc $dr,$hash$uimm3 */ 1340 { 1341 XC16X_INSN_ADDCRI, "addcri", "addc", 16, 1342 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1343 }, 1344 /* subc $dr,$hash$uimm3 */ 1345 { 1346 XC16X_INSN_SUBCRI, "subcri", "subc", 16, 1347 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1348 }, 1349 /* addcb $drb,$hash$uimm3 */ 1350 { 1351 XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16, 1352 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1353 }, 1354 /* subcb $drb,$hash$uimm3 */ 1355 { 1356 XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16, 1357 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1358 }, 1359 /* addc $reg8,$hash$uimm16 */ 1360 { 1361 XC16X_INSN_ADDCRIM, "addcrim", "addc", 32, 1362 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1363 }, 1364 /* subc $reg8,$hash$uimm16 */ 1365 { 1366 XC16X_INSN_SUBCRIM, "subcrim", "subc", 32, 1367 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1368 }, 1369 /* addcb $regb8,$hash$uimm8 */ 1370 { 1371 XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32, 1372 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1373 }, 1374 /* subcb $regb8,$hash$uimm8 */ 1375 { 1376 XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32, 1377 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1378 }, 1379 /* add $dr,$sr */ 1380 { 1381 XC16X_INSN_ADDR, "addr", "add", 16, 1382 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1383 }, 1384 /* sub $dr,$sr */ 1385 { 1386 XC16X_INSN_SUBR, "subr", "sub", 16, 1387 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1388 }, 1389 /* addb $drb,$srb */ 1390 { 1391 XC16X_INSN_ADDBR, "addbr", "addb", 16, 1392 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1393 }, 1394 /* subb $drb,$srb */ 1395 { 1396 XC16X_INSN_SUBBR, "subbr", "subb", 16, 1397 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1398 }, 1399 /* add $dr,[$sr2] */ 1400 { 1401 XC16X_INSN_ADD2, "add2", "add", 16, 1402 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1403 }, 1404 /* sub $dr,[$sr2] */ 1405 { 1406 XC16X_INSN_SUB2, "sub2", "sub", 16, 1407 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1408 }, 1409 /* addb $drb,[$sr2] */ 1410 { 1411 XC16X_INSN_ADDB2, "addb2", "addb", 16, 1412 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1413 }, 1414 /* subb $drb,[$sr2] */ 1415 { 1416 XC16X_INSN_SUBB2, "subb2", "subb", 16, 1417 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1418 }, 1419 /* add $dr,[$sr2+] */ 1420 { 1421 XC16X_INSN_ADD2I, "add2i", "add", 16, 1422 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1423 }, 1424 /* sub $dr,[$sr2+] */ 1425 { 1426 XC16X_INSN_SUB2I, "sub2i", "sub", 16, 1427 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1428 }, 1429 /* addb $drb,[$sr2+] */ 1430 { 1431 XC16X_INSN_ADDB2I, "addb2i", "addb", 16, 1432 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1433 }, 1434 /* subb $drb,[$sr2+] */ 1435 { 1436 XC16X_INSN_SUBB2I, "subb2i", "subb", 16, 1437 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1438 }, 1439 /* addc $dr,$sr */ 1440 { 1441 XC16X_INSN_ADDCR, "addcr", "addc", 16, 1442 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1443 }, 1444 /* subc $dr,$sr */ 1445 { 1446 XC16X_INSN_SUBCR, "subcr", "subc", 16, 1447 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1448 }, 1449 /* addcb $drb,$srb */ 1450 { 1451 XC16X_INSN_ADDBCR, "addbcr", "addcb", 16, 1452 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1453 }, 1454 /* subcb $drb,$srb */ 1455 { 1456 XC16X_INSN_SUBBCR, "subbcr", "subcb", 16, 1457 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1458 }, 1459 /* addc $dr,[$sr2] */ 1460 { 1461 XC16X_INSN_ADDCR2, "addcr2", "addc", 16, 1462 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1463 }, 1464 /* subc $dr,[$sr2] */ 1465 { 1466 XC16X_INSN_SUBCR2, "subcr2", "subc", 16, 1467 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1468 }, 1469 /* addcb $drb,[$sr2] */ 1470 { 1471 XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16, 1472 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1473 }, 1474 /* subcb $drb,[$sr2] */ 1475 { 1476 XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16, 1477 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1478 }, 1479 /* addc $dr,[$sr2+] */ 1480 { 1481 XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16, 1482 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1483 }, 1484 /* subc $dr,[$sr2+] */ 1485 { 1486 XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16, 1487 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1488 }, 1489 /* addcb $drb,[$sr2+] */ 1490 { 1491 XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16, 1492 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1493 }, 1494 /* subcb $drb,[$sr2+] */ 1495 { 1496 XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16, 1497 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1498 }, 1499 /* add $regmem8,$memgr8 */ 1500 { 1501 XC16X_INSN_ADDRM2, "addrm2", "add", 32, 1502 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1503 }, 1504 /* add $memgr8,$regmem8 */ 1505 { 1506 XC16X_INSN_ADDRM3, "addrm3", "add", 32, 1507 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1508 }, 1509 /* add $reg8,$memory */ 1510 { 1511 XC16X_INSN_ADDRM, "addrm", "add", 32, 1512 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1513 }, 1514 /* add $memory,$reg8 */ 1515 { 1516 XC16X_INSN_ADDRM1, "addrm1", "add", 32, 1517 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1518 }, 1519 /* sub $regmem8,$memgr8 */ 1520 { 1521 XC16X_INSN_SUBRM3, "subrm3", "sub", 32, 1522 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1523 }, 1524 /* sub $memgr8,$regmem8 */ 1525 { 1526 XC16X_INSN_SUBRM2, "subrm2", "sub", 32, 1527 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1528 }, 1529 /* sub $reg8,$memory */ 1530 { 1531 XC16X_INSN_SUBRM1, "subrm1", "sub", 32, 1532 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1533 }, 1534 /* sub $memory,$reg8 */ 1535 { 1536 XC16X_INSN_SUBRM, "subrm", "sub", 32, 1537 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1538 }, 1539 /* addb $regbmem8,$memgr8 */ 1540 { 1541 XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32, 1542 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1543 }, 1544 /* addb $memgr8,$regbmem8 */ 1545 { 1546 XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32, 1547 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1548 }, 1549 /* addb $regb8,$memory */ 1550 { 1551 XC16X_INSN_ADDBRM, "addbrm", "addb", 32, 1552 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1553 }, 1554 /* addb $memory,$regb8 */ 1555 { 1556 XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32, 1557 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1558 }, 1559 /* subb $regbmem8,$memgr8 */ 1560 { 1561 XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32, 1562 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1563 }, 1564 /* subb $memgr8,$regbmem8 */ 1565 { 1566 XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32, 1567 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1568 }, 1569 /* subb $regb8,$memory */ 1570 { 1571 XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32, 1572 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1573 }, 1574 /* subb $memory,$regb8 */ 1575 { 1576 XC16X_INSN_SUBBRM, "subbrm", "subb", 32, 1577 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1578 }, 1579 /* addc $regmem8,$memgr8 */ 1580 { 1581 XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32, 1582 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1583 }, 1584 /* addc $memgr8,$regmem8 */ 1585 { 1586 XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32, 1587 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1588 }, 1589 /* addc $reg8,$memory */ 1590 { 1591 XC16X_INSN_ADDCRM, "addcrm", "addc", 32, 1592 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1593 }, 1594 /* addc $memory,$reg8 */ 1595 { 1596 XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32, 1597 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1598 }, 1599 /* subc $regmem8,$memgr8 */ 1600 { 1601 XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32, 1602 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1603 }, 1604 /* subc $memgr8,$regmem8 */ 1605 { 1606 XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32, 1607 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1608 }, 1609 /* subc $reg8,$memory */ 1610 { 1611 XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32, 1612 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1613 }, 1614 /* subc $memory,$reg8 */ 1615 { 1616 XC16X_INSN_SUBCRM, "subcrm", "subc", 32, 1617 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1618 }, 1619 /* addcb $regbmem8,$memgr8 */ 1620 { 1621 XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32, 1622 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1623 }, 1624 /* addcb $memgr8,$regbmem8 */ 1625 { 1626 XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32, 1627 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1628 }, 1629 /* addcb $regb8,$memory */ 1630 { 1631 XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32, 1632 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1633 }, 1634 /* addcb $memory,$regb8 */ 1635 { 1636 XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32, 1637 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1638 }, 1639 /* subcb $regbmem8,$memgr8 */ 1640 { 1641 XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32, 1642 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1643 }, 1644 /* subcb $memgr8,$regbmem8 */ 1645 { 1646 XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32, 1647 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1648 }, 1649 /* subcb $regb8,$memory */ 1650 { 1651 XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32, 1652 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1653 }, 1654 /* subcb $memory,$regb8 */ 1655 { 1656 XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32, 1657 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1658 }, 1659 /* mul $src1,$src2 */ 1660 { 1661 XC16X_INSN_MULS, "muls", "mul", 16, 1662 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1663 }, 1664 /* mulu $src1,$src2 */ 1665 { 1666 XC16X_INSN_MULU, "mulu", "mulu", 16, 1667 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1668 }, 1669 /* div $srdiv */ 1670 { 1671 XC16X_INSN_DIV, "div", "div", 16, 1672 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1673 }, 1674 /* divl $srdiv */ 1675 { 1676 XC16X_INSN_DIVL, "divl", "divl", 16, 1677 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1678 }, 1679 /* divlu $srdiv */ 1680 { 1681 XC16X_INSN_DIVLU, "divlu", "divlu", 16, 1682 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1683 }, 1684 /* divu $srdiv */ 1685 { 1686 XC16X_INSN_DIVU, "divu", "divu", 16, 1687 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1688 }, 1689 /* cpl $dr */ 1690 { 1691 XC16X_INSN_CPL, "cpl", "cpl", 16, 1692 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1693 }, 1694 /* cplb $drb */ 1695 { 1696 XC16X_INSN_CPLB, "cplb", "cplb", 16, 1697 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1698 }, 1699 /* neg $dr */ 1700 { 1701 XC16X_INSN_NEG, "neg", "neg", 16, 1702 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1703 }, 1704 /* negb $drb */ 1705 { 1706 XC16X_INSN_NEGB, "negb", "negb", 16, 1707 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1708 }, 1709 /* and $dr,$sr */ 1710 { 1711 XC16X_INSN_ANDR, "andr", "and", 16, 1712 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1713 }, 1714 /* or $dr,$sr */ 1715 { 1716 XC16X_INSN_ORR, "orr", "or", 16, 1717 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1718 }, 1719 /* xor $dr,$sr */ 1720 { 1721 XC16X_INSN_XORR, "xorr", "xor", 16, 1722 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1723 }, 1724 /* andb $drb,$srb */ 1725 { 1726 XC16X_INSN_ANDBR, "andbr", "andb", 16, 1727 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1728 }, 1729 /* orb $drb,$srb */ 1730 { 1731 XC16X_INSN_ORBR, "orbr", "orb", 16, 1732 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1733 }, 1734 /* xorb $drb,$srb */ 1735 { 1736 XC16X_INSN_XORBR, "xorbr", "xorb", 16, 1737 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1738 }, 1739 /* and $dr,$hash$uimm3 */ 1740 { 1741 XC16X_INSN_ANDRI, "andri", "and", 16, 1742 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1743 }, 1744 /* or $dr,$hash$uimm3 */ 1745 { 1746 XC16X_INSN_ORRI, "orri", "or", 16, 1747 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1748 }, 1749 /* xor $dr,$hash$uimm3 */ 1750 { 1751 XC16X_INSN_XORRI, "xorri", "xor", 16, 1752 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1753 }, 1754 /* andb $drb,$hash$uimm3 */ 1755 { 1756 XC16X_INSN_ANDBRI, "andbri", "andb", 16, 1757 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1758 }, 1759 /* orb $drb,$hash$uimm3 */ 1760 { 1761 XC16X_INSN_ORBRI, "orbri", "orb", 16, 1762 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1763 }, 1764 /* xorb $drb,$hash$uimm3 */ 1765 { 1766 XC16X_INSN_XORBRI, "xorbri", "xorb", 16, 1767 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1768 }, 1769 /* and $reg8,$hash$uimm16 */ 1770 { 1771 XC16X_INSN_ANDRIM, "andrim", "and", 32, 1772 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1773 }, 1774 /* or $reg8,$hash$uimm16 */ 1775 { 1776 XC16X_INSN_ORRIM, "orrim", "or", 32, 1777 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1778 }, 1779 /* xor $reg8,$hash$uimm16 */ 1780 { 1781 XC16X_INSN_XORRIM, "xorrim", "xor", 32, 1782 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1783 }, 1784 /* andb $regb8,$hash$uimm8 */ 1785 { 1786 XC16X_INSN_ANDBRIM, "andbrim", "andb", 32, 1787 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1788 }, 1789 /* orb $regb8,$hash$uimm8 */ 1790 { 1791 XC16X_INSN_ORBRIM, "orbrim", "orb", 32, 1792 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1793 }, 1794 /* xorb $regb8,$hash$uimm8 */ 1795 { 1796 XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32, 1797 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1798 }, 1799 /* and $dr,[$sr2] */ 1800 { 1801 XC16X_INSN_AND2, "and2", "and", 16, 1802 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1803 }, 1804 /* or $dr,[$sr2] */ 1805 { 1806 XC16X_INSN_OR2, "or2", "or", 16, 1807 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1808 }, 1809 /* xor $dr,[$sr2] */ 1810 { 1811 XC16X_INSN_XOR2, "xor2", "xor", 16, 1812 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1813 }, 1814 /* andb $drb,[$sr2] */ 1815 { 1816 XC16X_INSN_ANDB2, "andb2", "andb", 16, 1817 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1818 }, 1819 /* orb $drb,[$sr2] */ 1820 { 1821 XC16X_INSN_ORB2, "orb2", "orb", 16, 1822 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1823 }, 1824 /* xorb $drb,[$sr2] */ 1825 { 1826 XC16X_INSN_XORB2, "xorb2", "xorb", 16, 1827 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1828 }, 1829 /* and $dr,[$sr2+] */ 1830 { 1831 XC16X_INSN_AND2I, "and2i", "and", 16, 1832 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1833 }, 1834 /* or $dr,[$sr2+] */ 1835 { 1836 XC16X_INSN_OR2I, "or2i", "or", 16, 1837 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1838 }, 1839 /* xor $dr,[$sr2+] */ 1840 { 1841 XC16X_INSN_XOR2I, "xor2i", "xor", 16, 1842 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1843 }, 1844 /* andb $drb,[$sr2+] */ 1845 { 1846 XC16X_INSN_ANDB2I, "andb2i", "andb", 16, 1847 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1848 }, 1849 /* orb $drb,[$sr2+] */ 1850 { 1851 XC16X_INSN_ORB2I, "orb2i", "orb", 16, 1852 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1853 }, 1854 /* xorb $drb,[$sr2+] */ 1855 { 1856 XC16X_INSN_XORB2I, "xorb2i", "xorb", 16, 1857 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1858 }, 1859 /* and $pof$reg8,$upof16 */ 1860 { 1861 XC16X_INSN_ANDPOFR, "andpofr", "and", 32, 1862 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1863 }, 1864 /* or $pof$reg8,$upof16 */ 1865 { 1866 XC16X_INSN_ORPOFR, "orpofr", "or", 32, 1867 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1868 }, 1869 /* xor $pof$reg8,$upof16 */ 1870 { 1871 XC16X_INSN_XORPOFR, "xorpofr", "xor", 32, 1872 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1873 }, 1874 /* andb $pof$regb8,$upof16 */ 1875 { 1876 XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32, 1877 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1878 }, 1879 /* orb $pof$regb8,$upof16 */ 1880 { 1881 XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32, 1882 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1883 }, 1884 /* xorb $pof$regb8,$upof16 */ 1885 { 1886 XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32, 1887 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1888 }, 1889 /* and $pof$upof16,$reg8 */ 1890 { 1891 XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32, 1892 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1893 }, 1894 /* or $pof$upof16,$reg8 */ 1895 { 1896 XC16X_INSN_ORRPOFR, "orrpofr", "or", 32, 1897 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1898 }, 1899 /* xor $pof$upof16,$reg8 */ 1900 { 1901 XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32, 1902 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1903 }, 1904 /* andb $pof$upof16,$regb8 */ 1905 { 1906 XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32, 1907 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1908 }, 1909 /* orb $pof$upof16,$regb8 */ 1910 { 1911 XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32, 1912 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1913 }, 1914 /* xorb $pof$upof16,$regb8 */ 1915 { 1916 XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32, 1917 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1918 }, 1919 /* and $regmem8,$memgr8 */ 1920 { 1921 XC16X_INSN_ANDRM2, "andrm2", "and", 32, 1922 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1923 }, 1924 /* and $memgr8,$regmem8 */ 1925 { 1926 XC16X_INSN_ANDRM3, "andrm3", "and", 32, 1927 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1928 }, 1929 /* and $reg8,$memory */ 1930 { 1931 XC16X_INSN_ANDRM, "andrm", "and", 32, 1932 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1933 }, 1934 /* and $memory,$reg8 */ 1935 { 1936 XC16X_INSN_ANDRM1, "andrm1", "and", 32, 1937 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1938 }, 1939 /* or $regmem8,$memgr8 */ 1940 { 1941 XC16X_INSN_ORRM3, "orrm3", "or", 32, 1942 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1943 }, 1944 /* or $memgr8,$regmem8 */ 1945 { 1946 XC16X_INSN_ORRM2, "orrm2", "or", 32, 1947 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1948 }, 1949 /* or $reg8,$memory */ 1950 { 1951 XC16X_INSN_ORRM1, "orrm1", "or", 32, 1952 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1953 }, 1954 /* or $memory,$reg8 */ 1955 { 1956 XC16X_INSN_ORRM, "orrm", "or", 32, 1957 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1958 }, 1959 /* xor $regmem8,$memgr8 */ 1960 { 1961 XC16X_INSN_XORRM3, "xorrm3", "xor", 32, 1962 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1963 }, 1964 /* xor $memgr8,$regmem8 */ 1965 { 1966 XC16X_INSN_XORRM2, "xorrm2", "xor", 32, 1967 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1968 }, 1969 /* xor $reg8,$memory */ 1970 { 1971 XC16X_INSN_XORRM1, "xorrm1", "xor", 32, 1972 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1973 }, 1974 /* xor $memory,$reg8 */ 1975 { 1976 XC16X_INSN_XORRM, "xorrm", "xor", 32, 1977 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1978 }, 1979 /* andb $regbmem8,$memgr8 */ 1980 { 1981 XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32, 1982 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1983 }, 1984 /* andb $memgr8,$regbmem8 */ 1985 { 1986 XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32, 1987 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1988 }, 1989 /* andb $regb8,$memory */ 1990 { 1991 XC16X_INSN_ANDBRM, "andbrm", "andb", 32, 1992 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1993 }, 1994 /* andb $memory,$regb8 */ 1995 { 1996 XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32, 1997 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 1998 }, 1999 /* orb $regbmem8,$memgr8 */ 2000 { 2001 XC16X_INSN_ORBRM3, "orbrm3", "orb", 32, 2002 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2003 }, 2004 /* orb $memgr8,$regbmem8 */ 2005 { 2006 XC16X_INSN_ORBRM2, "orbrm2", "orb", 32, 2007 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2008 }, 2009 /* orb $regb8,$memory */ 2010 { 2011 XC16X_INSN_ORBRM1, "orbrm1", "orb", 32, 2012 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2013 }, 2014 /* orb $memory,$regb8 */ 2015 { 2016 XC16X_INSN_ORBRM, "orbrm", "orb", 32, 2017 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2018 }, 2019 /* xorb $regbmem8,$memgr8 */ 2020 { 2021 XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32, 2022 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2023 }, 2024 /* xorb $memgr8,$regbmem8 */ 2025 { 2026 XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32, 2027 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2028 }, 2029 /* xorb $regb8,$memory */ 2030 { 2031 XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32, 2032 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2033 }, 2034 /* xorb $memory,$regb8 */ 2035 { 2036 XC16X_INSN_XORBRM, "xorbrm", "xorb", 32, 2037 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2038 }, 2039 /* mov $dr,$sr */ 2040 { 2041 XC16X_INSN_MOVR, "movr", "mov", 16, 2042 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2043 }, 2044 /* movb $drb,$srb */ 2045 { 2046 XC16X_INSN_MOVRB, "movrb", "movb", 16, 2047 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2048 }, 2049 /* mov $dri,$hash$u4 */ 2050 { 2051 XC16X_INSN_MOVRI, "movri", "mov", 16, 2052 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2053 }, 2054 /* movb $srb,$hash$u4 */ 2055 { 2056 XC16X_INSN_MOVBRI, "movbri", "movb", 16, 2057 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2058 }, 2059 /* mov $reg8,$hash$uimm16 */ 2060 { 2061 XC16X_INSN_MOVI, "movi", "mov", 32, 2062 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2063 }, 2064 /* movb $regb8,$hash$uimm8 */ 2065 { 2066 XC16X_INSN_MOVBI, "movbi", "movb", 32, 2067 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2068 }, 2069 /* mov $dr,[$sr] */ 2070 { 2071 XC16X_INSN_MOVR2, "movr2", "mov", 16, 2072 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2073 }, 2074 /* movb $drb,[$sr] */ 2075 { 2076 XC16X_INSN_MOVBR2, "movbr2", "movb", 16, 2077 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2078 }, 2079 /* mov [$sr],$dr */ 2080 { 2081 XC16X_INSN_MOVRI2, "movri2", "mov", 16, 2082 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2083 }, 2084 /* movb [$sr],$drb */ 2085 { 2086 XC16X_INSN_MOVBRI2, "movbri2", "movb", 16, 2087 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2088 }, 2089 /* mov [-$sr],$dr */ 2090 { 2091 XC16X_INSN_MOVRI3, "movri3", "mov", 16, 2092 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2093 }, 2094 /* movb [-$sr],$drb */ 2095 { 2096 XC16X_INSN_MOVBRI3, "movbri3", "movb", 16, 2097 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2098 }, 2099 /* mov $dr,[$sr+] */ 2100 { 2101 XC16X_INSN_MOV2I, "mov2i", "mov", 16, 2102 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2103 }, 2104 /* movb $drb,[$sr+] */ 2105 { 2106 XC16X_INSN_MOVB2I, "movb2i", "movb", 16, 2107 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2108 }, 2109 /* mov [$dr],[$sr] */ 2110 { 2111 XC16X_INSN_MOV6I, "mov6i", "mov", 16, 2112 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2113 }, 2114 /* movb [$dr],[$sr] */ 2115 { 2116 XC16X_INSN_MOVB6I, "movb6i", "movb", 16, 2117 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2118 }, 2119 /* mov [$dr+],[$sr] */ 2120 { 2121 XC16X_INSN_MOV7I, "mov7i", "mov", 16, 2122 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2123 }, 2124 /* movb [$dr+],[$sr] */ 2125 { 2126 XC16X_INSN_MOVB7I, "movb7i", "movb", 16, 2127 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2128 }, 2129 /* mov [$dr],[$sr+] */ 2130 { 2131 XC16X_INSN_MOV8I, "mov8i", "mov", 16, 2132 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2133 }, 2134 /* movb [$dr],[$sr+] */ 2135 { 2136 XC16X_INSN_MOVB8I, "movb8i", "movb", 16, 2137 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2138 }, 2139 /* mov $dr,[$sr+$hash$uimm16] */ 2140 { 2141 XC16X_INSN_MOV9I, "mov9i", "mov", 32, 2142 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2143 }, 2144 /* movb $drb,[$sr+$hash$uimm16] */ 2145 { 2146 XC16X_INSN_MOVB9I, "movb9i", "movb", 32, 2147 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2148 }, 2149 /* mov [$sr+$hash$uimm16],$dr */ 2150 { 2151 XC16X_INSN_MOV10I, "mov10i", "mov", 32, 2152 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2153 }, 2154 /* movb [$sr+$hash$uimm16],$drb */ 2155 { 2156 XC16X_INSN_MOVB10I, "movb10i", "movb", 32, 2157 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2158 }, 2159 /* mov [$src2],$memory */ 2160 { 2161 XC16X_INSN_MOVRI11, "movri11", "mov", 32, 2162 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2163 }, 2164 /* movb [$src2],$memory */ 2165 { 2166 XC16X_INSN_MOVBRI11, "movbri11", "movb", 32, 2167 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2168 }, 2169 /* mov $memory,[$src2] */ 2170 { 2171 XC16X_INSN_MOVRI12, "movri12", "mov", 32, 2172 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2173 }, 2174 /* movb $memory,[$src2] */ 2175 { 2176 XC16X_INSN_MOVBRI12, "movbri12", "movb", 32, 2177 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2178 }, 2179 /* mov $regoff8,$hash$pof$upof16 */ 2180 { 2181 XC16X_INSN_MOVEHM5, "movehm5", "mov", 32, 2182 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2183 }, 2184 /* mov $regoff8,$hash$pag$upag16 */ 2185 { 2186 XC16X_INSN_MOVEHM6, "movehm6", "mov", 32, 2187 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2188 }, 2189 /* mov $regoff8,$hash$segm$useg16 */ 2190 { 2191 XC16X_INSN_MOVEHM7, "movehm7", "mov", 32, 2192 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2193 }, 2194 /* mov $regoff8,$hash$sof$usof16 */ 2195 { 2196 XC16X_INSN_MOVEHM8, "movehm8", "mov", 32, 2197 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2198 }, 2199 /* movb $regb8,$hash$pof$uimm8 */ 2200 { 2201 XC16X_INSN_MOVEHM9, "movehm9", "movb", 32, 2202 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2203 }, 2204 /* movb $regoff8,$hash$pag$uimm8 */ 2205 { 2206 XC16X_INSN_MOVEHM10, "movehm10", "movb", 32, 2207 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2208 }, 2209 /* mov $regoff8,$pof$upof16 */ 2210 { 2211 XC16X_INSN_MOVRMP, "movrmp", "mov", 32, 2212 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2213 }, 2214 /* movb $regb8,$pof$upof16 */ 2215 { 2216 XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32, 2217 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2218 }, 2219 /* mov $regoff8,$pag$upag16 */ 2220 { 2221 XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32, 2222 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2223 }, 2224 /* movb $regb8,$pag$upag16 */ 2225 { 2226 XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32, 2227 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2228 }, 2229 /* mov $pof$upof16,$regoff8 */ 2230 { 2231 XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32, 2232 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2233 }, 2234 /* movb $pof$upof16,$regb8 */ 2235 { 2236 XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32, 2237 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2238 }, 2239 /* mov $dri,$hash$pof$u4 */ 2240 { 2241 XC16X_INSN_MOVEHM1, "movehm1", "mov", 16, 2242 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2243 }, 2244 /* movb $srb,$hash$pof$u4 */ 2245 { 2246 XC16X_INSN_MOVEHM2, "movehm2", "movb", 16, 2247 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2248 }, 2249 /* mov $dri,$hash$pag$u4 */ 2250 { 2251 XC16X_INSN_MOVEHM3, "movehm3", "mov", 16, 2252 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2253 }, 2254 /* movb $srb,$hash$pag$u4 */ 2255 { 2256 XC16X_INSN_MOVEHM4, "movehm4", "movb", 16, 2257 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2258 }, 2259 /* mov $regmem8,$memgr8 */ 2260 { 2261 XC16X_INSN_MVE12, "mve12", "mov", 32, 2262 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2263 }, 2264 /* mov $memgr8,$regmem8 */ 2265 { 2266 XC16X_INSN_MVE13, "mve13", "mov", 32, 2267 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2268 }, 2269 /* mov $reg8,$memory */ 2270 { 2271 XC16X_INSN_MOVER12, "mover12", "mov", 32, 2272 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2273 }, 2274 /* mov $memory,$reg8 */ 2275 { 2276 XC16X_INSN_MVR13, "mvr13", "mov", 32, 2277 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2278 }, 2279 /* movb $regbmem8,$memgr8 */ 2280 { 2281 XC16X_INSN_MVER12, "mver12", "movb", 32, 2282 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2283 }, 2284 /* movb $memgr8,$regbmem8 */ 2285 { 2286 XC16X_INSN_MVER13, "mver13", "movb", 32, 2287 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2288 }, 2289 /* movb $regb8,$memory */ 2290 { 2291 XC16X_INSN_MOVR12, "movr12", "movb", 32, 2292 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2293 }, 2294 /* movb $memory,$regb8 */ 2295 { 2296 XC16X_INSN_MOVR13, "movr13", "movb", 32, 2297 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2298 }, 2299 /* movbs $sr,$drb */ 2300 { 2301 XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16, 2302 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2303 }, 2304 /* movbz $sr,$drb */ 2305 { 2306 XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16, 2307 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2308 }, 2309 /* movbs $regmem8,$pof$upof16 */ 2310 { 2311 XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32, 2312 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2313 }, 2314 /* movbs $pof$upof16,$regbmem8 */ 2315 { 2316 XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32, 2317 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2318 }, 2319 /* movbz $reg8,$pof$upof16 */ 2320 { 2321 XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32, 2322 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2323 }, 2324 /* movbz $pof$upof16,$regb8 */ 2325 { 2326 XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32, 2327 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2328 }, 2329 /* movbs $regmem8,$memgr8 */ 2330 { 2331 XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32, 2332 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2333 }, 2334 /* movbs $memgr8,$regbmem8 */ 2335 { 2336 XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32, 2337 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2338 }, 2339 /* movbs $reg8,$memory */ 2340 { 2341 XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32, 2342 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2343 }, 2344 /* movbs $memory,$regb8 */ 2345 { 2346 XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32, 2347 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2348 }, 2349 /* movbz $regmem8,$memgr8 */ 2350 { 2351 XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32, 2352 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2353 }, 2354 /* movbz $memgr8,$regbmem8 */ 2355 { 2356 XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32, 2357 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2358 }, 2359 /* movbz $reg8,$memory */ 2360 { 2361 XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32, 2362 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2363 }, 2364 /* movbz $memory,$regb8 */ 2365 { 2366 XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32, 2367 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2368 }, 2369 /* movbs $sr,$drb */ 2370 { 2371 XC16X_INSN_MOVRBS, "movrbs", "movbs", 16, 2372 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2373 }, 2374 /* movbz $sr,$drb */ 2375 { 2376 XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16, 2377 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2378 }, 2379 /* jmpa+ $extcond,$caddr */ 2380 { 2381 XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32, 2382 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2383 }, 2384 /* jmpa $extcond,$caddr */ 2385 { 2386 XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32, 2387 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2388 }, 2389 /* jmpa- $extcond,$caddr */ 2390 { 2391 XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32, 2392 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2393 }, 2394 /* jmpi $icond,[$sr] */ 2395 { 2396 XC16X_INSN_JMPI, "jmpi", "jmpi", 16, 2397 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2398 }, 2399 /* jmpr $cond,$rel */ 2400 { 2401 XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16, 2402 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2403 }, 2404 /* jmpr $cond,$rel */ 2405 { 2406 XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16, 2407 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2408 }, 2409 /* jmpr $cond,$rel */ 2410 { 2411 XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16, 2412 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2413 }, 2414 /* jmpr $cond,$rel */ 2415 { 2416 XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16, 2417 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2418 }, 2419 /* jmpr $cond,$rel */ 2420 { 2421 XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16, 2422 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2423 }, 2424 /* jmpr $cond,$rel */ 2425 { 2426 XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16, 2427 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2428 }, 2429 /* jmpr $cond,$rel */ 2430 { 2431 XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16, 2432 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2433 }, 2434 /* jmpr $cond,$rel */ 2435 { 2436 XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16, 2437 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2438 }, 2439 /* jmpr $cond,$rel */ 2440 { 2441 XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16, 2442 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2443 }, 2444 /* jmpr $cond,$rel */ 2445 { 2446 XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16, 2447 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2448 }, 2449 /* jmpr $cond,$rel */ 2450 { 2451 XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16, 2452 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2453 }, 2454 /* jmpr $cond,$rel */ 2455 { 2456 XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16, 2457 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2458 }, 2459 /* jmpr $cond,$rel */ 2460 { 2461 XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16, 2462 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2463 }, 2464 /* jmpr $cond,$rel */ 2465 { 2466 XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16, 2467 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2468 }, 2469 /* jmpr $cond,$rel */ 2470 { 2471 XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16, 2472 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2473 }, 2474 /* jmpr $cond,$rel */ 2475 { 2476 XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16, 2477 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2478 }, 2479 /* jmpr $cond,$rel */ 2480 { 2481 XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16, 2482 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2483 }, 2484 /* jmpr $cond,$rel */ 2485 { 2486 XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16, 2487 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2488 }, 2489 /* jmpr $cond,$rel */ 2490 { 2491 XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16, 2492 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2493 }, 2494 /* jmpr $cond,$rel */ 2495 { 2496 XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16, 2497 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2498 }, 2499 /* jmps $hash$segm$useg8,$hash$sof$usof16 */ 2500 { 2501 XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32, 2502 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2503 }, 2504 /* jmps $seg,$caddr */ 2505 { 2506 XC16X_INSN_JMPS, "jmps", "jmps", 32, 2507 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2508 }, 2509 /* jb $genreg$dot$qlobit,$relhi */ 2510 { 2511 XC16X_INSN_JB, "jb", "jb", 32, 2512 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2513 }, 2514 /* jbc $genreg$dot$qlobit,$relhi */ 2515 { 2516 XC16X_INSN_JBC, "jbc", "jbc", 32, 2517 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2518 }, 2519 /* jnb $genreg$dot$qlobit,$relhi */ 2520 { 2521 XC16X_INSN_JNB, "jnb", "jnb", 32, 2522 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2523 }, 2524 /* jnbs $genreg$dot$qlobit,$relhi */ 2525 { 2526 XC16X_INSN_JNBS, "jnbs", "jnbs", 32, 2527 { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2528 }, 2529 /* calla+ $extcond,$caddr */ 2530 { 2531 XC16X_INSN_CALLA0, "calla0", "calla+", 32, 2532 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2533 }, 2534 /* calla $extcond,$caddr */ 2535 { 2536 XC16X_INSN_CALLA1, "calla1", "calla", 32, 2537 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2538 }, 2539 /* calla- $extcond,$caddr */ 2540 { 2541 XC16X_INSN_CALLA_, "calla-", "calla-", 32, 2542 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2543 }, 2544 /* calli $icond,[$sr] */ 2545 { 2546 XC16X_INSN_CALLI, "calli", "calli", 16, 2547 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2548 }, 2549 /* callr $rel */ 2550 { 2551 XC16X_INSN_CALLR, "callr", "callr", 16, 2552 { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2553 }, 2554 /* calls $hash$segm$useg8,$hash$sof$usof16 */ 2555 { 2556 XC16X_INSN_CALLSEG, "callseg", "calls", 32, 2557 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2558 }, 2559 /* calls $seg,$caddr */ 2560 { 2561 XC16X_INSN_CALLS, "calls", "calls", 32, 2562 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2563 }, 2564 /* pcall $reg8,$caddr */ 2565 { 2566 XC16X_INSN_PCALL, "pcall", "pcall", 32, 2567 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2568 }, 2569 /* trap $hash$uimm7 */ 2570 { 2571 XC16X_INSN_TRAP, "trap", "trap", 16, 2572 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2573 }, 2574 /* ret */ 2575 { 2576 XC16X_INSN_RET, "ret", "ret", 16, 2577 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2578 }, 2579 /* rets */ 2580 { 2581 XC16X_INSN_RETS, "rets", "rets", 16, 2582 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2583 }, 2584 /* retp $reg8 */ 2585 { 2586 XC16X_INSN_RETP, "retp", "retp", 16, 2587 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2588 }, 2589 /* reti */ 2590 { 2591 XC16X_INSN_RETI, "reti", "reti", 16, 2592 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2593 }, 2594 /* pop $reg8 */ 2595 { 2596 XC16X_INSN_POP, "pop", "pop", 16, 2597 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2598 }, 2599 /* push $reg8 */ 2600 { 2601 XC16X_INSN_PUSH, "push", "push", 16, 2602 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2603 }, 2604 /* scxt $reg8,$hash$uimm16 */ 2605 { 2606 XC16X_INSN_SCXTI, "scxti", "scxt", 32, 2607 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2608 }, 2609 /* scxt $reg8,$pof$upof16 */ 2610 { 2611 XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32, 2612 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2613 }, 2614 /* scxt $regmem8,$memgr8 */ 2615 { 2616 XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32, 2617 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2618 }, 2619 /* scxt $reg8,$memory */ 2620 { 2621 XC16X_INSN_SCXTM, "scxtm", "scxt", 32, 2622 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2623 }, 2624 /* nop */ 2625 { 2626 XC16X_INSN_NOP, "nop", "nop", 16, 2627 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2628 }, 2629 /* srst */ 2630 { 2631 XC16X_INSN_SRSTM, "srstm", "srst", 32, 2632 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2633 }, 2634 /* idle */ 2635 { 2636 XC16X_INSN_IDLEM, "idlem", "idle", 32, 2637 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2638 }, 2639 /* pwrdn */ 2640 { 2641 XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32, 2642 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2643 }, 2644 /* diswdt */ 2645 { 2646 XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32, 2647 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2648 }, 2649 /* enwdt */ 2650 { 2651 XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32, 2652 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2653 }, 2654 /* einit */ 2655 { 2656 XC16X_INSN_EINITM, "einitm", "einit", 32, 2657 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2658 }, 2659 /* srvwdt */ 2660 { 2661 XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32, 2662 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2663 }, 2664 /* sbrk */ 2665 { 2666 XC16X_INSN_SBRK, "sbrk", "sbrk", 16, 2667 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2668 }, 2669 /* atomic $hash$uimm2 */ 2670 { 2671 XC16X_INSN_ATOMIC, "atomic", "atomic", 16, 2672 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2673 }, 2674 /* extr $hash$uimm2 */ 2675 { 2676 XC16X_INSN_EXTR, "extr", "extr", 16, 2677 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2678 }, 2679 /* extp $sr,$hash$uimm2 */ 2680 { 2681 XC16X_INSN_EXTP, "extp", "extp", 16, 2682 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2683 }, 2684 /* extp $hash$pagenum,$hash$uimm2 */ 2685 { 2686 XC16X_INSN_EXTP1, "extp1", "extp", 32, 2687 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2688 }, 2689 /* extp $hash$pag$upag16,$hash$uimm2 */ 2690 { 2691 XC16X_INSN_EXTPG1, "extpg1", "extp", 32, 2692 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2693 }, 2694 /* extpr $sr,$hash$uimm2 */ 2695 { 2696 XC16X_INSN_EXTPR, "extpr", "extpr", 16, 2697 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2698 }, 2699 /* extpr $hash$pagenum,$hash$uimm2 */ 2700 { 2701 XC16X_INSN_EXTPR1, "extpr1", "extpr", 32, 2702 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2703 }, 2704 /* exts $sr,$hash$uimm2 */ 2705 { 2706 XC16X_INSN_EXTS, "exts", "exts", 16, 2707 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2708 }, 2709 /* exts $hash$seghi8,$hash$uimm2 */ 2710 { 2711 XC16X_INSN_EXTS1, "exts1", "exts", 32, 2712 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2713 }, 2714 /* extsr $sr,$hash$uimm2 */ 2715 { 2716 XC16X_INSN_EXTSR, "extsr", "extsr", 16, 2717 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2718 }, 2719 /* extsr $hash$seghi8,$hash$uimm2 */ 2720 { 2721 XC16X_INSN_EXTSR1, "extsr1", "extsr", 32, 2722 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2723 }, 2724 /* prior $dr,$sr */ 2725 { 2726 XC16X_INSN_PRIOR, "prior", "prior", 16, 2727 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2728 }, 2729 /* bclr $RegNam */ 2730 { 2731 XC16X_INSN_BCLR18, "bclr18", "bclr", 16, 2732 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2733 }, 2734 /* bclr $reg8$dot$qbit */ 2735 { 2736 XC16X_INSN_BCLR0, "bclr0", "bclr", 16, 2737 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2738 }, 2739 /* bclr $reg8$dot$qbit */ 2740 { 2741 XC16X_INSN_BCLR1, "bclr1", "bclr", 16, 2742 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2743 }, 2744 /* bclr $reg8$dot$qbit */ 2745 { 2746 XC16X_INSN_BCLR2, "bclr2", "bclr", 16, 2747 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2748 }, 2749 /* bclr $reg8$dot$qbit */ 2750 { 2751 XC16X_INSN_BCLR3, "bclr3", "bclr", 16, 2752 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2753 }, 2754 /* bclr $reg8$dot$qbit */ 2755 { 2756 XC16X_INSN_BCLR4, "bclr4", "bclr", 16, 2757 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2758 }, 2759 /* bclr $reg8$dot$qbit */ 2760 { 2761 XC16X_INSN_BCLR5, "bclr5", "bclr", 16, 2762 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2763 }, 2764 /* bclr $reg8$dot$qbit */ 2765 { 2766 XC16X_INSN_BCLR6, "bclr6", "bclr", 16, 2767 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2768 }, 2769 /* bclr $reg8$dot$qbit */ 2770 { 2771 XC16X_INSN_BCLR7, "bclr7", "bclr", 16, 2772 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2773 }, 2774 /* bclr $reg8$dot$qbit */ 2775 { 2776 XC16X_INSN_BCLR8, "bclr8", "bclr", 16, 2777 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2778 }, 2779 /* bclr $reg8$dot$qbit */ 2780 { 2781 XC16X_INSN_BCLR9, "bclr9", "bclr", 16, 2782 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2783 }, 2784 /* bclr $reg8$dot$qbit */ 2785 { 2786 XC16X_INSN_BCLR10, "bclr10", "bclr", 16, 2787 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2788 }, 2789 /* bclr $reg8$dot$qbit */ 2790 { 2791 XC16X_INSN_BCLR11, "bclr11", "bclr", 16, 2792 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2793 }, 2794 /* bclr $reg8$dot$qbit */ 2795 { 2796 XC16X_INSN_BCLR12, "bclr12", "bclr", 16, 2797 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2798 }, 2799 /* bclr $reg8$dot$qbit */ 2800 { 2801 XC16X_INSN_BCLR13, "bclr13", "bclr", 16, 2802 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2803 }, 2804 /* bclr $reg8$dot$qbit */ 2805 { 2806 XC16X_INSN_BCLR14, "bclr14", "bclr", 16, 2807 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2808 }, 2809 /* bclr $reg8$dot$qbit */ 2810 { 2811 XC16X_INSN_BCLR15, "bclr15", "bclr", 16, 2812 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2813 }, 2814 /* bset $RegNam */ 2815 { 2816 XC16X_INSN_BSET19, "bset19", "bset", 16, 2817 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2818 }, 2819 /* bset $reg8$dot$qbit */ 2820 { 2821 XC16X_INSN_BSET0, "bset0", "bset", 16, 2822 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2823 }, 2824 /* bset $reg8$dot$qbit */ 2825 { 2826 XC16X_INSN_BSET1, "bset1", "bset", 16, 2827 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2828 }, 2829 /* bset $reg8$dot$qbit */ 2830 { 2831 XC16X_INSN_BSET2, "bset2", "bset", 16, 2832 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2833 }, 2834 /* bset $reg8$dot$qbit */ 2835 { 2836 XC16X_INSN_BSET3, "bset3", "bset", 16, 2837 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2838 }, 2839 /* bset $reg8$dot$qbit */ 2840 { 2841 XC16X_INSN_BSET4, "bset4", "bset", 16, 2842 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2843 }, 2844 /* bset $reg8$dot$qbit */ 2845 { 2846 XC16X_INSN_BSET5, "bset5", "bset", 16, 2847 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2848 }, 2849 /* bset $reg8$dot$qbit */ 2850 { 2851 XC16X_INSN_BSET6, "bset6", "bset", 16, 2852 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2853 }, 2854 /* bset $reg8$dot$qbit */ 2855 { 2856 XC16X_INSN_BSET7, "bset7", "bset", 16, 2857 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2858 }, 2859 /* bset $reg8$dot$qbit */ 2860 { 2861 XC16X_INSN_BSET8, "bset8", "bset", 16, 2862 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2863 }, 2864 /* bset $reg8$dot$qbit */ 2865 { 2866 XC16X_INSN_BSET9, "bset9", "bset", 16, 2867 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2868 }, 2869 /* bset $reg8$dot$qbit */ 2870 { 2871 XC16X_INSN_BSET10, "bset10", "bset", 16, 2872 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2873 }, 2874 /* bset $reg8$dot$qbit */ 2875 { 2876 XC16X_INSN_BSET11, "bset11", "bset", 16, 2877 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2878 }, 2879 /* bset $reg8$dot$qbit */ 2880 { 2881 XC16X_INSN_BSET12, "bset12", "bset", 16, 2882 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2883 }, 2884 /* bset $reg8$dot$qbit */ 2885 { 2886 XC16X_INSN_BSET13, "bset13", "bset", 16, 2887 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2888 }, 2889 /* bset $reg8$dot$qbit */ 2890 { 2891 XC16X_INSN_BSET14, "bset14", "bset", 16, 2892 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2893 }, 2894 /* bset $reg8$dot$qbit */ 2895 { 2896 XC16X_INSN_BSET15, "bset15", "bset", 16, 2897 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2898 }, 2899 /* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */ 2900 { 2901 XC16X_INSN_BMOV, "bmov", "bmov", 32, 2902 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2903 }, 2904 /* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */ 2905 { 2906 XC16X_INSN_BMOVN, "bmovn", "bmovn", 32, 2907 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2908 }, 2909 /* band $reghi8$dot$qhibit,$reg8$dot$qlobit */ 2910 { 2911 XC16X_INSN_BAND, "band", "band", 32, 2912 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2913 }, 2914 /* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */ 2915 { 2916 XC16X_INSN_BOR, "bor", "bor", 32, 2917 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2918 }, 2919 /* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */ 2920 { 2921 XC16X_INSN_BXOR, "bxor", "bxor", 32, 2922 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2923 }, 2924 /* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */ 2925 { 2926 XC16X_INSN_BCMP, "bcmp", "bcmp", 32, 2927 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2928 }, 2929 /* bfldl $reg8,$hash$mask8,$hash$datahi8 */ 2930 { 2931 XC16X_INSN_BFLDL, "bfldl", "bfldl", 32, 2932 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2933 }, 2934 /* bfldh $reg8,$hash$masklo8,$hash$data8 */ 2935 { 2936 XC16X_INSN_BFLDH, "bfldh", "bfldh", 32, 2937 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2938 }, 2939 /* cmp $src1,$src2 */ 2940 { 2941 XC16X_INSN_CMPR, "cmpr", "cmp", 16, 2942 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2943 }, 2944 /* cmpb $drb,$srb */ 2945 { 2946 XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16, 2947 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2948 }, 2949 /* cmp $src1,$hash$uimm3 */ 2950 { 2951 XC16X_INSN_CMPRI, "cmpri", "cmp", 16, 2952 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2953 }, 2954 /* cmpb $drb,$hash$uimm3 */ 2955 { 2956 XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16, 2957 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2958 }, 2959 /* cmp $reg8,$hash$uimm16 */ 2960 { 2961 XC16X_INSN_CMPI, "cmpi", "cmp", 32, 2962 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2963 }, 2964 /* cmpb $regb8,$hash$uimm8 */ 2965 { 2966 XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32, 2967 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2968 }, 2969 /* cmp $dr,[$sr2] */ 2970 { 2971 XC16X_INSN_CMPR2, "cmpr2", "cmp", 16, 2972 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2973 }, 2974 /* cmpb $drb,[$sr2] */ 2975 { 2976 XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16, 2977 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2978 }, 2979 /* cmp $dr,[$sr2+] */ 2980 { 2981 XC16X_INSN_CMP2I, "cmp2i", "cmp", 16, 2982 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2983 }, 2984 /* cmpb $drb,[$sr2+] */ 2985 { 2986 XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16, 2987 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2988 }, 2989 /* cmp $reg8,$pof$upof16 */ 2990 { 2991 XC16X_INSN_CMP04, "cmp04", "cmp", 32, 2992 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2993 }, 2994 /* cmpb $regb8,$pof$upof16 */ 2995 { 2996 XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32, 2997 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 2998 }, 2999 /* cmp $regmem8,$memgr8 */ 3000 { 3001 XC16X_INSN_CMP004, "cmp004", "cmp", 32, 3002 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3003 }, 3004 /* cmp $reg8,$memory */ 3005 { 3006 XC16X_INSN_CMP0004, "cmp0004", "cmp", 32, 3007 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3008 }, 3009 /* cmpb $regbmem8,$memgr8 */ 3010 { 3011 XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32, 3012 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3013 }, 3014 /* cmpb $regb8,$memory */ 3015 { 3016 XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32, 3017 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3018 }, 3019 /* cmpd1 $sr,$hash$uimm4 */ 3020 { 3021 XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16, 3022 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3023 }, 3024 /* cmpd2 $sr,$hash$uimm4 */ 3025 { 3026 XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16, 3027 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3028 }, 3029 /* cmpi1 $sr,$hash$uimm4 */ 3030 { 3031 XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16, 3032 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3033 }, 3034 /* cmpi2 $sr,$hash$uimm4 */ 3035 { 3036 XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16, 3037 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3038 }, 3039 /* cmpd1 $reg8,$hash$uimm16 */ 3040 { 3041 XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32, 3042 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3043 }, 3044 /* cmpd2 $reg8,$hash$uimm16 */ 3045 { 3046 XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32, 3047 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3048 }, 3049 /* cmpi1 $reg8,$hash$uimm16 */ 3050 { 3051 XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32, 3052 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3053 }, 3054 /* cmpi2 $reg8,$hash$uimm16 */ 3055 { 3056 XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32, 3057 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3058 }, 3059 /* cmpd1 $reg8,$pof$upof16 */ 3060 { 3061 XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32, 3062 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3063 }, 3064 /* cmpd2 $reg8,$pof$upof16 */ 3065 { 3066 XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32, 3067 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3068 }, 3069 /* cmpi1 $reg8,$pof$upof16 */ 3070 { 3071 XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32, 3072 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3073 }, 3074 /* cmpi2 $reg8,$pof$upof16 */ 3075 { 3076 XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32, 3077 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3078 }, 3079 /* cmpd1 $regmem8,$memgr8 */ 3080 { 3081 XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32, 3082 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3083 }, 3084 /* cmpd2 $regmem8,$memgr8 */ 3085 { 3086 XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32, 3087 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3088 }, 3089 /* cmpi1 $regmem8,$memgr8 */ 3090 { 3091 XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32, 3092 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3093 }, 3094 /* cmpi2 $regmem8,$memgr8 */ 3095 { 3096 XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32, 3097 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3098 }, 3099 /* cmpd1 $reg8,$memory */ 3100 { 3101 XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32, 3102 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3103 }, 3104 /* cmpd2 $reg8,$memory */ 3105 { 3106 XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32, 3107 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3108 }, 3109 /* cmpi1 $reg8,$memory */ 3110 { 3111 XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32, 3112 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3113 }, 3114 /* cmpi2 $reg8,$memory */ 3115 { 3116 XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32, 3117 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3118 }, 3119 /* shl $dr,$sr */ 3120 { 3121 XC16X_INSN_SHLR, "shlr", "shl", 16, 3122 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3123 }, 3124 /* shr $dr,$sr */ 3125 { 3126 XC16X_INSN_SHRR, "shrr", "shr", 16, 3127 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3128 }, 3129 /* rol $dr,$sr */ 3130 { 3131 XC16X_INSN_ROLR, "rolr", "rol", 16, 3132 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3133 }, 3134 /* ror $dr,$sr */ 3135 { 3136 XC16X_INSN_RORR, "rorr", "ror", 16, 3137 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3138 }, 3139 /* ashr $dr,$sr */ 3140 { 3141 XC16X_INSN_ASHRR, "ashrr", "ashr", 16, 3142 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3143 }, 3144 /* shl $sr,$hash$uimm4 */ 3145 { 3146 XC16X_INSN_SHLRI, "shlri", "shl", 16, 3147 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3148 }, 3149 /* shr $sr,$hash$uimm4 */ 3150 { 3151 XC16X_INSN_SHRRI, "shrri", "shr", 16, 3152 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3153 }, 3154 /* rol $sr,$hash$uimm4 */ 3155 { 3156 XC16X_INSN_ROLRI, "rolri", "rol", 16, 3157 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3158 }, 3159 /* ror $sr,$hash$uimm4 */ 3160 { 3161 XC16X_INSN_RORRI, "rorri", "ror", 16, 3162 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3163 }, 3164 /* ashr $sr,$hash$uimm4 */ 3165 { 3166 XC16X_INSN_ASHRRI, "ashrri", "ashr", 16, 3167 { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } } 3168 }, 3169 }; 3170 3171 #undef OP 3172 #undef A 3173 3174 /* Initialize anything needed to be done once, before any cpu_open call. */ 3175 3176 static void 3177 init_tables (void) 3178 { 3179 } 3180 3181 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 3182 static void build_hw_table (CGEN_CPU_TABLE *); 3183 static void build_ifield_table (CGEN_CPU_TABLE *); 3184 static void build_operand_table (CGEN_CPU_TABLE *); 3185 static void build_insn_table (CGEN_CPU_TABLE *); 3186 static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *); 3187 3188 /* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name. */ 3189 3190 static const CGEN_MACH * 3191 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 3192 { 3193 while (table->name) 3194 { 3195 if (strcmp (name, table->bfd_name) == 0) 3196 return table; 3197 ++table; 3198 } 3199 abort (); 3200 } 3201 3202 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */ 3203 3204 static void 3205 build_hw_table (CGEN_CPU_TABLE *cd) 3206 { 3207 int i; 3208 int machs = cd->machs; 3209 const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0]; 3210 /* MAX_HW is only an upper bound on the number of selected entries. 3211 However each entry is indexed by it's enum so there can be holes in 3212 the table. */ 3213 const CGEN_HW_ENTRY **selected = 3214 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 3215 3216 cd->hw_table.init_entries = init; 3217 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 3218 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 3219 /* ??? For now we just use machs to determine which ones we want. */ 3220 for (i = 0; init[i].name != NULL; ++i) 3221 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 3222 & machs) 3223 selected[init[i].type] = &init[i]; 3224 cd->hw_table.entries = selected; 3225 cd->hw_table.num_entries = MAX_HW; 3226 } 3227 3228 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */ 3229 3230 static void 3231 build_ifield_table (CGEN_CPU_TABLE *cd) 3232 { 3233 cd->ifld_table = & xc16x_cgen_ifld_table[0]; 3234 } 3235 3236 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. */ 3237 3238 static void 3239 build_operand_table (CGEN_CPU_TABLE *cd) 3240 { 3241 int i; 3242 int machs = cd->machs; 3243 const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0]; 3244 /* MAX_OPERANDS is only an upper bound on the number of selected entries. 3245 However each entry is indexed by it's enum so there can be holes in 3246 the table. */ 3247 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 3248 3249 cd->operand_table.init_entries = init; 3250 cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 3251 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 3252 /* ??? For now we just use mach to determine which ones we want. */ 3253 for (i = 0; init[i].name != NULL; ++i) 3254 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 3255 & machs) 3256 selected[init[i].type] = &init[i]; 3257 cd->operand_table.entries = selected; 3258 cd->operand_table.num_entries = MAX_OPERANDS; 3259 } 3260 3261 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table. 3262 ??? This could leave out insns not supported by the specified mach/isa, 3263 but that would cause errors like "foo only supported by bar" to become 3264 "unknown insn", so for now we include all insns and require the app to 3265 do the checking later. 3266 ??? On the other hand, parsing of such insns may require their hardware or 3267 operand elements to be in the table [which they mightn't be]. */ 3268 3269 static void 3270 build_insn_table (CGEN_CPU_TABLE *cd) 3271 { 3272 int i; 3273 const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0]; 3274 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 3275 3276 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 3277 for (i = 0; i < MAX_INSNS; ++i) 3278 insns[i].base = &ib[i]; 3279 cd->insn_table.init_entries = insns; 3280 cd->insn_table.entry_size = sizeof (CGEN_IBASE); 3281 cd->insn_table.num_init_entries = MAX_INSNS; 3282 } 3283 3284 /* Subroutine of xc16x_cgen_cpu_open to rebuild the tables. */ 3285 3286 static void 3287 xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 3288 { 3289 int i; 3290 CGEN_BITSET *isas = cd->isas; 3291 unsigned int machs = cd->machs; 3292 3293 cd->int_insn_p = CGEN_INT_INSN_P; 3294 3295 /* Data derived from the isa spec. */ 3296 #define UNSET (CGEN_SIZE_UNKNOWN + 1) 3297 cd->default_insn_bitsize = UNSET; 3298 cd->base_insn_bitsize = UNSET; 3299 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 3300 cd->max_insn_bitsize = 0; 3301 for (i = 0; i < MAX_ISAS; ++i) 3302 if (cgen_bitset_contains (isas, i)) 3303 { 3304 const CGEN_ISA *isa = & xc16x_cgen_isa_table[i]; 3305 3306 /* Default insn sizes of all selected isas must be 3307 equal or we set the result to 0, meaning "unknown". */ 3308 if (cd->default_insn_bitsize == UNSET) 3309 cd->default_insn_bitsize = isa->default_insn_bitsize; 3310 else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 3311 ; /* This is ok. */ 3312 else 3313 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 3314 3315 /* Base insn sizes of all selected isas must be equal 3316 or we set the result to 0, meaning "unknown". */ 3317 if (cd->base_insn_bitsize == UNSET) 3318 cd->base_insn_bitsize = isa->base_insn_bitsize; 3319 else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 3320 ; /* This is ok. */ 3321 else 3322 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 3323 3324 /* Set min,max insn sizes. */ 3325 if (isa->min_insn_bitsize < cd->min_insn_bitsize) 3326 cd->min_insn_bitsize = isa->min_insn_bitsize; 3327 if (isa->max_insn_bitsize > cd->max_insn_bitsize) 3328 cd->max_insn_bitsize = isa->max_insn_bitsize; 3329 } 3330 3331 /* Data derived from the mach spec. */ 3332 for (i = 0; i < MAX_MACHS; ++i) 3333 if (((1 << i) & machs) != 0) 3334 { 3335 const CGEN_MACH *mach = & xc16x_cgen_mach_table[i]; 3336 3337 if (mach->insn_chunk_bitsize != 0) 3338 { 3339 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 3340 { 3341 fprintf (stderr, "xc16x_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", 3342 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 3343 abort (); 3344 } 3345 3346 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 3347 } 3348 } 3349 3350 /* Determine which hw elements are used by MACH. */ 3351 build_hw_table (cd); 3352 3353 /* Build the ifield table. */ 3354 build_ifield_table (cd); 3355 3356 /* Determine which operands are used by MACH/ISA. */ 3357 build_operand_table (cd); 3358 3359 /* Build the instruction table. */ 3360 build_insn_table (cd); 3361 } 3362 3363 /* Initialize a cpu table and return a descriptor. 3364 It's much like opening a file, and must be the first function called. 3365 The arguments are a set of (type/value) pairs, terminated with 3366 CGEN_CPU_OPEN_END. 3367 3368 Currently supported values: 3369 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 3370 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 3371 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 3372 CGEN_CPU_OPEN_ENDIAN: specify endian choice 3373 CGEN_CPU_OPEN_END: terminates arguments 3374 3375 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 3376 precluded. */ 3377 3378 CGEN_CPU_DESC 3379 xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 3380 { 3381 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 3382 static int init_p; 3383 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 3384 unsigned int machs = 0; /* 0 = "unspecified" */ 3385 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 3386 va_list ap; 3387 3388 if (! init_p) 3389 { 3390 init_tables (); 3391 init_p = 1; 3392 } 3393 3394 memset (cd, 0, sizeof (*cd)); 3395 3396 va_start (ap, arg_type); 3397 while (arg_type != CGEN_CPU_OPEN_END) 3398 { 3399 switch (arg_type) 3400 { 3401 case CGEN_CPU_OPEN_ISAS : 3402 isas = va_arg (ap, CGEN_BITSET *); 3403 break; 3404 case CGEN_CPU_OPEN_MACHS : 3405 machs = va_arg (ap, unsigned int); 3406 break; 3407 case CGEN_CPU_OPEN_BFDMACH : 3408 { 3409 const char *name = va_arg (ap, const char *); 3410 const CGEN_MACH *mach = 3411 lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name); 3412 3413 machs |= 1 << mach->num; 3414 break; 3415 } 3416 case CGEN_CPU_OPEN_ENDIAN : 3417 endian = va_arg (ap, enum cgen_endian); 3418 break; 3419 default : 3420 fprintf (stderr, "xc16x_cgen_cpu_open: unsupported argument `%d'\n", 3421 arg_type); 3422 abort (); /* ??? return NULL? */ 3423 } 3424 arg_type = va_arg (ap, enum cgen_cpu_open_arg); 3425 } 3426 va_end (ap); 3427 3428 /* Mach unspecified means "all". */ 3429 if (machs == 0) 3430 machs = (1 << MAX_MACHS) - 1; 3431 /* Base mach is always selected. */ 3432 machs |= 1; 3433 if (endian == CGEN_ENDIAN_UNKNOWN) 3434 { 3435 /* ??? If target has only one, could have a default. */ 3436 fprintf (stderr, "xc16x_cgen_cpu_open: no endianness specified\n"); 3437 abort (); 3438 } 3439 3440 cd->isas = cgen_bitset_copy (isas); 3441 cd->machs = machs; 3442 cd->endian = endian; 3443 /* FIXME: for the sparc case we can determine insn-endianness statically. 3444 The worry here is where both data and insn endian can be independently 3445 chosen, in which case this function will need another argument. 3446 Actually, will want to allow for more arguments in the future anyway. */ 3447 cd->insn_endian = endian; 3448 3449 /* Table (re)builder. */ 3450 cd->rebuild_tables = xc16x_cgen_rebuild_tables; 3451 xc16x_cgen_rebuild_tables (cd); 3452 3453 /* Default to not allowing signed overflow. */ 3454 cd->signed_overflow_ok_p = 0; 3455 3456 return (CGEN_CPU_DESC) cd; 3457 } 3458 3459 /* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 3460 MACH_NAME is the bfd name of the mach. */ 3461 3462 CGEN_CPU_DESC 3463 xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 3464 { 3465 return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 3466 CGEN_CPU_OPEN_ENDIAN, endian, 3467 CGEN_CPU_OPEN_END); 3468 } 3469 3470 /* Close a cpu table. 3471 ??? This can live in a machine independent file, but there's currently 3472 no place to put this file (there's no libcgen). libopcodes is the wrong 3473 place as some simulator ports use this but they don't use libopcodes. */ 3474 3475 void 3476 xc16x_cgen_cpu_close (CGEN_CPU_DESC cd) 3477 { 3478 unsigned int i; 3479 const CGEN_INSN *insns; 3480 3481 if (cd->macro_insn_table.init_entries) 3482 { 3483 insns = cd->macro_insn_table.init_entries; 3484 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 3485 if (CGEN_INSN_RX ((insns))) 3486 regfree (CGEN_INSN_RX (insns)); 3487 } 3488 3489 if (cd->insn_table.init_entries) 3490 { 3491 insns = cd->insn_table.init_entries; 3492 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 3493 if (CGEN_INSN_RX (insns)) 3494 regfree (CGEN_INSN_RX (insns)); 3495 } 3496 3497 if (cd->macro_insn_table.init_entries) 3498 free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 3499 3500 if (cd->insn_table.init_entries) 3501 free ((CGEN_INSN *) cd->insn_table.init_entries); 3502 3503 if (cd->hw_table.entries) 3504 free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 3505 3506 if (cd->operand_table.entries) 3507 free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 3508 3509 free (cd); 3510 } 3511 3512
