| /external/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.cpp | 23 for (const MCPhysReg *CSR =
25 unsigned Reg = *CSR;
26 ++CSR)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenExtract.cpp | 87 ConstantInt *CSL = 0, *CSR = 0, *CM = 0;
94 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
101 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
108 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0);
118 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
125 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
132 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)),
139 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)),
152 uint32_t SR = CSR->getZExtValue();
|
| HexagonFrameLowering.cpp | 94 // stack frame | (aligned) | | (CSR, spills, etc.) |FP|
232 bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR) {
261 if (CSR[R])
331 BitVector CSR(Hexagon::NUM_TARGET_REGS);
333 CSR[*P] = true;
336 if (needsStackFrame(I, CSR))
[all...] |
| HexagonVLIWPacketizer.cpp | 316 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
317 if (MI->modifiesRegister(*CSR, TRI))
[all...] |
| /external/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 143 for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
144 LiveRegs.addReg(*CSR);
|
| RegisterClassInfo.cpp | 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
52 if (Update || CSR != CalleeSaved) {
53 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
54 // overlapping CSR.
57 for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
59 CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
62 CalleeSaved = CSR;
77 /// registers filtered out. Volatile registers come first followed by CSR
78 /// aliases ordered according to the CSR order specified by the target.
107 // PhysReg aliases a CSR, save it for later
[all...] |
| MachineFunction.cpp | 619 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
620 BV.set(*CSR);
[all...] |
| RegAllocPBQP.cpp | 547 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
548 for (unsigned i = 0; CSR[i] != 0; ++i)
549 if (TRI.regsOverlap(reg, CSR[i]))
|
| RegAllocGreedy.cpp | 99 CSRFirstTimeCost("regalloc-csr-first-time-cost",
845 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
846 if (CSR == 0)
[all...] |
| /device/google/contexthub/firmware/src/platform/stm32f4xx/ |
| pwr.c | 51 volatile uint32_t CSR;
61 volatile uint32_t CSR;
158 static uint32_t pwrParseCsr(uint32_t csr)
162 if (csr & RCC_CSR_LPWRRSTF)
164 if (csr & RCC_CSR_WWDGRSTF)
166 if (csr & RCC_CSR_IWDGRSTF)
168 if (csr & RCC_CSR_SFTRSTF)
170 if (csr & RCC_CSR_PORRSTF)
172 if (csr & RCC_CSR_PINRSTF)
174 if (csr & RCC_CSR_BORRSTF
[all...] |
| bl.c | 81 volatile uint32_t CSR;
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| lm32-opc.c | 397 /* rcsr $r2,$csr */
400 { { MNEM, ' ', OP (R2), ',', OP (CSR), 0 } },
481 /* wcsr $csr,$r1 */
484 { { MNEM, ' ', OP (CSR), ',', OP (R1), 0 } },
|
| lm32-opinst.c | 150 { INPUT, "csr", HW_H_CSR, CGEN_MODE_SI, OP_ENT (CSR), 0, 0 },
|
| /external/llvm/include/llvm/ADT/ |
| Triple.h | 129 CSR,
|
| /external/llvm/lib/Support/ |
| Triple.cpp | 149 case CSR: return "csr";
409 .Case("csr", Triple::CSR)
[all...] |
| /external/clang/lib/Sema/ |
| SemaChecking.cpp | [all...] |
| /external/harfbuzz_ng/src/ |
| hb-ot-shape-complex-indic-table.cc | 357 /* 17C8 */ _(M,R), _(RS,T), _(RS,T), _(SM,T),_(CSR,T), _(CK,T), _(SM,T), _(SM,T),
438 /* 1B00 */ _(Bi,T), _(Bi,T), _(Bi,T),_(CSR,T), _(Vs,R), _(VI,x), _(VI,x), _(VI,x),
457 /* 1B80 */ _(Bi,T),_(CSR,T), _(Vs,R), _(VI,x), _(VI,x), _(VI,x), _(VI,x), _(VI,x),
[all...] |
