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    Searched refs:Cand (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Transforms/Scalar/
LoopLoadElimination.cpp 93 const StoreToLoadForwardingCandidate &Cand) {
94 OS << *Cand.Store << " -->\n";
95 OS.indent(2) << *Cand.Load << "\n";
210 for (const auto &Cand : Candidates) {
215 LoadToSingleCand.insert(std::make_pair(Cand.Load, &Cand));
225 if (Cand.Store->getParent() == OtherCand->Store->getParent() &&
226 Cand.isDependenceDistanceOfOne(PSE) &&
229 if (getInstrIndex(OtherCand->Store) < getInstrIndex(Cand.Store))
230 OtherCand = &Cand;
    [all...]
  /external/llvm/lib/CodeGen/
MachineScheduler.cpp     [all...]
RegAllocGreedy.cpp 350 void growRegion(GlobalSplitCandidate &Cand);
    [all...]
  /external/clang/lib/Sema/
SemaOverload.cpp     [all...]
SemaLookup.cpp     [all...]
  /external/llvm/include/llvm/CodeGen/
MachineScheduler.h 848 void traceCandidate(const SchedCandidate &Cand);
896 void tryCandidate(SchedCandidate &Cand,
957 void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
959 void pickNodeFromQueue(SchedCandidate &Cand);
  /external/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 146 MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
796 MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
797 const MachineInstr *First = Cand.Instrs.front();
805 for (const MachineInstr *MI : Cand.Instrs) {
836 MachineInstr *LatestMI = Cand.Instrs[Cand.LatestMIIdx];
846 if (Cand.CanMergeToLSDouble)
849 if (!Merged && Cand.CanMergeToLSMulti)
857 iterator EarliestI(Cand.Instrs[Cand.EarliestMIIdx])
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  /external/llvm/utils/TableGen/
CodeGenRegisters.cpp 421 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
423 if (Cand == this || getSubRegIndex(Cand))
425 // Check if each component of Cand is already a sub-register.
429 assert(!Cand->ExplicitSubRegs.empty() &&
431 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) {
432 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j]))
440 // If some Cand sub-register is not part of this register, or if Cand only
445 // Each part of Cand is a sub-register of this. Make the full Cand als
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonBitSimplify.cpp     [all...]

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