| /external/clang/test/Modules/ |
| macro-hiding.cpp | 88 #ifdef D1
89 #include "d1.h"
100 #if defined(A1) || defined(B2) || defined(C1) || defined(D1) || defined(E1) || defined(E2)
|
| macro-reexport.cpp | 23 #include "e2.h" // undefines d1's macro
25 #elif defined(D1)
26 #include "e1.h" // undefines c1's macro but not d1's macro
27 #include "d1.h"
29 #include "e2.h" // undefines d1's macro
35 // e2 undefines d1's macro, which overrides c1's macro.
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| metacore21ext.s | 4 MOVL RAWZ,[D1.1++]
6 MOVL RABX,[D1.2++]
8 MOVL RADX,[D1.3++]
|
| metacore21-invalid.s | 4 SETL [D0.0+D1.0],A0.0,A1.0
5 SETL [D0.0+D0.1],D0.2,D1.2
7 ASL D0.0,D1.0,D0.0
|
| metacore12.s | 4 ADD D0Re0,D0.7,D1.7
9 ADD D1Re0,D1.7,A1.7
10 ADD D1.7,D1Re0,A1LbP
11 ADD D1.7,D1Re0,A0FrP
12 ADD D1.7,D1.7,RD
19 ADDT D1.7,D1.7,#0x8000
20 MOV D1.7,#0xffff
27 ADDLE D1Re0,D0Re0,D1.
[all...] |
| metacore21.d | 12 .*: 0001de01 ADD D0Re0,D0\.7,D1\.7
17 .*: 0101ce01 ADD D1Re0,D1\.7,A1\.7
18 .*: 01380201 ADD D1\.7,D1Re0,A1LbP
19 .*: 01383201 ADD D1\.7,D1Re0,A0FrP
20 .*: 0139e001 ADD D1\.7,D1\.7,RD
27 .*: 033c0001 ADDT D1\.7,D1\.7,#0x8000
28 .*: 033ffffc MOV D1\.7,#0xffff
33 .*: 04001e3b ADDGT D0Re0,D0Re0,D1\.
[all...] |
| metacore21.s | 4 ADD D0Re0,D0.7,D1.7
9 ADD D1Re0,D1.7,A1.7
10 ADD D1.7,D1Re0,A1LbP
11 ADD D1.7,D1Re0,A0FrP
12 ADD D1.7,D1.7,RD
19 ADDT D1.7,D1.7,#0x8000
20 MOV D1.7,#0xffff
25 ADDGT D0Re0,D0Re0,D1.
[all...] |
| metacore12.d | 12 .*: 0001de01 ADD D0Re0,D0\.7,D1\.7
17 .*: 0101ce01 ADD D1Re0,D1\.7,A1\.7
18 .*: 01380201 ADD D1\.7,D1Re0,A1LbP
19 .*: 01383201 ADD D1\.7,D1Re0,A0FrP
20 .*: 0139e001 ADD D1\.7,D1\.7,RD
27 .*: 033c0001 ADDT D1\.7,D1\.7,#0x8000
28 .*: 033ffffc MOV D1\.7,#0xffff
35 .*: 04001e5d ADDLE D1Re0,D0Re0,D1\.
[all...] |
| metafpu21.d | 14 .*: 0401df21 F ADD FX\.0,D0\.7,D1\.7
22 .*: 04101f23 F ADDEQ FX\.2,D0Re0,D1\.7
30 .*: 0419df3d F ADDLE FX\.3,D0\.7,D1\.7
35 .*: 0421df21 F ADD FX\.4,D0\.7,D1\.7
43 .*: 04381f23 F ADDEQ FX\.7,D0Re0,D1\.7
51 .*: 0451df3d F ADDLE FX\.10,D0\.7,D1\.7
56 .*: 0479df21 F ADD FX\.15,D0\.7,D1\.7
58 .*: 05000f22 F ADDEQ FX\.0,D1Re0,D1\.7
60 .*: 0501c13c F ADDLE FX\.0,D1\.7,D1Re0
61 .*: 0501d12b F ADDMI FX\.0,D1\.7,D0Re
[all...] |
| /external/clang/test/CodeGen/ |
| mips64-class-return.cpp | 14 class D1 : public B1 {
24 extern D1 gd1;
33 D1 foo2(void) {
|
| /external/mesa3d/src/glsl/glcpp/tests/ |
| 067-nested-ifdef-ifndef.c | 1 #define D1
14 #ifndef D1
24 #ifdef D1
|
| /external/clang/test/CXX/class.derived/class.member.lookup/ |
| p8.cpp | 12 struct D1 : public Base {};
15 struct Derived : public D1, public D2 {
21 d.D1::Foo();
22 d.D1::Member = 17;
26 D1::Foo();
27 D1::Member = 42;
28 this->D1::Foo();
29 this->D1::Member = 42;
|
| /external/clang/test/Misc/ |
| diag-line-wrapping.cpp | 5 struct D1 : B {};
7 struct DD : D1, D2 {
12 // CHECK: struct DD -> struct D1 -> struct B
|
| /prebuilts/gcc/darwin-x86/x86/x86_64-linux-android-4.9/lib/gcc/x86_64-linux-android/4.9/include/ |
| lwpintrin.h | 64 #define __lwpval32(D2, D1, F) \
65 (__builtin_ia32_lwpval32 ((unsigned int) (D2), (unsigned int) (D1), \
68 #define __lwpval64(D2, D1, F) \
69 (__builtin_ia32_lwpval64 ((unsigned long long) (D2), (unsigned int) (D1), \
90 #define __lwpins32(D2, D1, F) \
91 (__builtin_ia32_lwpins32 ((unsigned int) (D2), (unsigned int) (D1), \
94 #define __lwpins64(D2, D1, F) \
95 (__builtin_ia32_lwpins64 ((unsigned long long) (D2), (unsigned int) (D1), \
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/lib/gcc/x86_64-linux/4.8/include/ |
| lwpintrin.h | 62 #define __lwpval32(D2, D1, F) \
63 (__builtin_ia32_lwpval32 ((unsigned int) (D2), (unsigned int) (D1), \
66 #define __lwpval64(D2, D1, F) \
67 (__builtin_ia32_lwpval64 ((unsigned long long) (D2), (unsigned int) (D1), \
88 #define __lwpins32(D2, D1, F) \
89 (__builtin_ia32_lwpins32 ((unsigned int) (D2), (unsigned int) (D1), \
92 #define __lwpins64(D2, D1, F) \
93 (__builtin_ia32_lwpins64 ((unsigned long long) (D2), (unsigned int) (D1), \
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/lib/gcc/x86_64-linux/4.8/include/ |
| lwpintrin.h | 62 #define __lwpval32(D2, D1, F) \
63 (__builtin_ia32_lwpval32 ((unsigned int) (D2), (unsigned int) (D1), \
66 #define __lwpval64(D2, D1, F) \
67 (__builtin_ia32_lwpval64 ((unsigned long long) (D2), (unsigned int) (D1), \
88 #define __lwpins32(D2, D1, F) \
89 (__builtin_ia32_lwpins32 ((unsigned int) (D2), (unsigned int) (D1), \
92 #define __lwpins64(D2, D1, F) \
93 (__builtin_ia32_lwpins64 ((unsigned long long) (D2), (unsigned int) (D1), \
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/include/ |
| lwpintrin.h | 62 #define __lwpval32(D2, D1, F) \
63 (__builtin_ia32_lwpval32 ((unsigned int) (D2), (unsigned int) (D1), \
66 #define __lwpval64(D2, D1, F) \
67 (__builtin_ia32_lwpval64 ((unsigned long long) (D2), (unsigned int) (D1), \
88 #define __lwpins32(D2, D1, F) \
89 (__builtin_ia32_lwpins32 ((unsigned int) (D2), (unsigned int) (D1), \
92 #define __lwpins64(D2, D1, F) \
93 (__builtin_ia32_lwpins64 ((unsigned long long) (D2), (unsigned int) (D1), \
|
| /prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/lib/gcc/x86_64-linux-android/4.9/include/ |
| lwpintrin.h | 64 #define __lwpval32(D2, D1, F) \
65 (__builtin_ia32_lwpval32 ((unsigned int) (D2), (unsigned int) (D1), \
68 #define __lwpval64(D2, D1, F) \
69 (__builtin_ia32_lwpval64 ((unsigned long long) (D2), (unsigned int) (D1), \
90 #define __lwpins32(D2, D1, F) \
91 (__builtin_ia32_lwpins32 ((unsigned int) (D2), (unsigned int) (D1), \
94 #define __lwpins64(D2, D1, F) \
95 (__builtin_ia32_lwpins64 ((unsigned long long) (D2), (unsigned int) (D1), \
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic6x/ |
| sploop-bad-5.s | 6 spmaskr D1,D1
|
| /external/clang/test/SemaTemplate/ |
| class-template-id-2.cpp | 16 struct D1 {
|
| /external/valgrind/cachegrind/tests/ |
| chdir.stderr.exp | 10 D1 misses:
12 D1 miss rate:
|
| dlclose.stderr.exp | 10 D1 misses:
12 D1 miss rate:
|
| notpower2.stderr.exp | 10 D1 misses:
12 D1 miss rate:
|
| wrap5.stderr.exp | 10 D1 misses:
12 D1 miss rate:
|
| /external/valgrind/cachegrind/tests/x86/ |
| fpu-28-108.stderr.exp | 10 D1 misses:
12 D1 miss rate:
|
