| /art/test/065-mismatched-implements/src/ |
| Defs.java | 17 public interface Defs {
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| Base.java | 17 public class Base implements Defs {
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| /art/test/066-mismatched-super/src/ |
| Base.java | 17 public class Base extends Defs {
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| Defs.java | 17 public abstract class Defs {
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| /art/test/066-mismatched-super/src2/ |
| Defs.java | 17 public interface Defs {
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| /art/test/065-mismatched-implements/src2/ |
| Defs.java | 17 public abstract class Defs {
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| /external/skia/src/svg/parser/ |
| SkSVGDefs.h | 16 DECLARE_SVG_INFO(Defs);
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| SkSVGDefs.cpp | 12 DEFINE_SVG_NO_INFO(Defs)
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| /external/lzma/CPP/7zip/Archive/7z/ |
| 7zItem.h | 95 CBoolVector Defs;
100 Defs.ClearAndSetSize(newSize);
106 Defs.Clear();
112 Defs.ReserveDown();
116 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; }
121 CBoolVector Defs;
126 Defs.Clear();
132 Defs.ReserveDown();
138 if (index < Defs.Size() && Defs[index])
[all...] |
| 7zOut.cpp | 335 for (i = 0; i < digests.Defs.Size(); i++)
336 if (digests.Defs[i])
342 if (numDefined == digests.Defs.Size())
347 WriteBoolVector(digests.Defs);
349 for (i = 0; i < digests.Defs.Size(); i++)
350 if (digests.Defs[i])
444 digests2.Defs.Add(digests.Defs[digestIndex]);
495 for (i = 0; i < v.Defs.Size(); i++)
496 if (v.Defs[i])
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenMux.cpp | 63 BitVector Defs, Uses;
64 DefUseInfo() : Defs(), Uses() {}
65 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
87 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
118 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
120 // First, get the implicit defs and uses for this instruction.
125 expandReg(*R++, Defs);
130 // Look over all operands, and collect explicit defs and uses.
135 BitVector &Set = Mo->isDef() ? Defs : Uses;
145 BitVector Defs(NR), Uses(NR)
[all...] |
| HexagonExpandCondsets.cpp | 166 bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses);
292 SmallVector<MachineInstr*,8> Defs;
299 Defs.push_back(MI);
303 Defs.push_back(MI);
306 for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
307 MachineInstr *MI = Defs[i];
322 /// processes, there may be defs present in the instruction sequence that have
435 SmallVector<RegisterRef,2> Defs;
438 Defs.push_back(RegisterRef(Op));
440 for (unsigned i = 0, n = Defs.size(); i < n; ++i)
[all...] |
| HexagonBitSimplify.cpp | 158 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
227 RegisterSet Defs;
229 getInstrDefs(I, Defs);
231 NewAVs.insert(Defs);
247 RegisterSet &Defs) {
254 Defs.insert(R);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 46 SmallSet<unsigned, 4> &Defs,
57 SmallSet<unsigned, 4> &Defs,
87 Defs.insert(*Subreg);
121 SmallSet<unsigned, 4> &Defs,
136 if (Uses.count(DstReg) || Defs.count(SrcReg))
178 SmallSet<unsigned, 4> Defs;
191 Defs.clear();
193 TrackDefUses(MI, Defs, Uses, TRI);
234 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
244 TrackDefUses(NMI, Defs, Uses, TRI)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCBoolRetToInt.cpp | 62 SmallPtrSet<Value *, 8> Defs;
65 Defs.insert(V);
71 if (Defs.insert(Op).second)
74 return Defs;
193 auto Defs = findAllDefs(U);
196 if (!std::any_of(Defs.begin(), Defs.end(), isa<Instruction, Value *>))
202 for (const auto &V : Defs)
206 for (const auto &V : Defs)
217 for (const auto &V : Defs)
[all...] |
| /external/llvm/utils/TableGen/ |
| CTagsEmitter.cpp | 67 const auto &Defs = Records.getDefs();
70 Tags.reserve(Classes.size() + Defs.size());
73 for (const auto &D : Defs)
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 40 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
41 Defs[Hexagon::LC0].insert(Unconditional);
44 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
45 Defs[Hexagon::LC1].insert(Unconditional);
113 Defs[R].insert(PredSense(PredReg, isTrue));
152 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue));
165 Defs[*SRI].insert(PredSense(PredReg, isTrue));
302 if (Branches) // FIXME: should "Defs.count(Hexagon::PC)" be here too?
330 if (!Defs.count(P) || LatePreds.count(P)) {
344 if (LatePreds.count(P) > 1 || Defs.count(P))
[all...] |
| /external/lzma/C/ |
| 7z.h | 77 Byte *Defs; /* MSB 0 bit numbering */
83 Byte *Defs; /* MSB 0 bit numbering */
90 #define SzBitWithVals_Check(p, i) ((p)->Defs && ((p)->Defs[(i) >> 3] & (0x80 >> ((i) & 7))) != 0)
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| /frameworks/compile/mclinker/include/mcld/MC/ |
| ZOption.h | 24 Defs,
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| /external/llvm/lib/CodeGen/ |
| MachineCopyPropagation.cpp | 72 const DestList& Defs = SI->second;
73 for (DestList::const_iterator I = Defs.begin(), E = Defs.end();
231 SmallVector<unsigned, 2> Defs;
248 Defs.push_back(Reg);
261 // Treat undef use like defs for copy propagation but not for
268 Defs.push_back(Reg);
299 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
300 unsigned Reg = Defs[i];
314 // If MBB doesn't have successors, delete the copies whose defs are not used
[all...] |
| LiveVariables.cpp | 229 /// implicit defs to a machine instruction if there was an earlier def of its
444 SmallVectorImpl<unsigned> &Defs) {
483 Defs.push_back(Reg); // Remember this def.
487 SmallVectorImpl<unsigned> &Defs) {
488 while (!Defs.empty()) {
489 unsigned Reg = Defs.back();
490 Defs.pop_back();
501 SmallVectorImpl<unsigned> &Defs) {
552 // Process all defs.
558 HandlePhysRegDef(MOReg, MI, Defs);
[all...] |
| MachineInstrBundle.cpp | 110 /// bundle, and it copies externally visible defs and uses to the BUNDLE
134 SmallVector<MachineOperand*, 4> Defs;
141 Defs.push_back(&MO);
166 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
167 MachineOperand &MO = *Defs[i];
194 Defs.clear();
276 // Both defs and uses can read virtual registers.
283 // Only defs can write.
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| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 160 SmallVectorImpl<unsigned> &Defs);
161 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
179 void runOnInstr(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
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| /packages/apps/Music/src/com/android/music/ |
| MusicBrowserActivity.java | 30 implements MusicUtils.Defs {
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| /external/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 75 /// This function sets all caller-saved registers in Defs.
78 /// This function sets all unallocatable registers in Defs.
96 BitVector Defs, Uses;
150 /// Update Defs and Uses. Return true if there exist dependences that
152 /// Defs.
160 SmallPtrSet<ValueType, 4> Uses, Defs;
296 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
302 // If MI is a call, add RA to Defs to prevent users of RA from going into
305 Defs.set(Mips::RA);
311 Defs.reset(Mips::AT)
[all...] |
