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  /external/libvpx/config/arm/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/arm-neon/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/arm64/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/generic/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/mips32/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/mips32-dspr2/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/mips64/
vpx_config.h 29 #define HAVE_SSSE3 0
  /external/libvpx/config/x86/
vpx_config.h 29 #define HAVE_SSSE3 1
  /external/libvpx/config/x86_64/
vpx_config.h 29 #define HAVE_SSSE3 1
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/armv7a/
vpx_config.h 28 #define HAVE_SSSE3 0
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/armv7a-neon/
vpx_config.h 28 #define HAVE_SSSE3 0
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/generic/
vpx_config.h 28 #define HAVE_SSSE3 0
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/mips/
vpx_config.h 28 #define HAVE_SSSE3 0
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/mips-dspr2/
vpx_config.h 28 #define HAVE_SSSE3 0
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/x86/
vpx_config.h 28 #define HAVE_SSSE3 1
vpx_config.asm 16 HAVE_SSSE3 equ 1
  /external/libvpx/libvpx/vpx_dsp/
vpx_dsp.mk 44 DSP_SRCS-$(HAVE_SSSE3) += x86/intrapred_ssse3.asm
45 DSP_SRCS-$(HAVE_SSSE3) += x86/vpx_subpixel_8t_ssse3.asm
74 DSP_SRCS-$(HAVE_SSSE3) += x86/vpx_subpixel_8t_ssse3.asm
75 DSP_SRCS-$(HAVE_SSSE3) += x86/vpx_subpixel_bilinear_ssse3.asm
77 DSP_SRCS-$(HAVE_SSSE3) += x86/vpx_subpixel_8t_intrin_ssse3.c
176 DSP_SRCS-$(HAVE_SSSE3) += x86/fwd_txfm_ssse3_x86_64.asm
196 DSP_SRCS-$(HAVE_SSSE3) += x86/inv_txfm_ssse3_x86_64.asm
251 DSP_SRCS-$(HAVE_SSSE3) += x86/quantize_ssse3_x86_64.asm
271 DSP_SRCS-$(HAVE_SSSE3) += x86/sad_ssse3.asm
  /external/libvpx/libvpx/test/
test_intra_pred_speed.cc 197 #if HAVE_SSSE3 && CONFIG_USE_X86INC
202 #endif // HAVE_SSSE3 && CONFIG_USE_X86INC
250 #if HAVE_SSSE3 && CONFIG_USE_X86INC
255 #endif // HAVE_SSSE3 && CONFIG_USE_X86INC
300 #if HAVE_SSSE3 && CONFIG_USE_X86INC
306 #endif // HAVE_SSSE3 && CONFIG_USE_X86INC
359 #if HAVE_SSSE3 && CONFIG_USE_X86INC
365 #endif // HAVE_SSSE3 && CONFIG_USE_X86INC
quantize_test.cc 177 #if HAVE_SSSE3
181 #endif // HAVE_SSSE3
partial_idct_test.cc 298 #if HAVE_SSSE3 && CONFIG_USE_X86INC && ARCH_X86_64 && \
  /external/libvpx/libvpx/vp9/
vp9cx.mk 113 VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_quantize_ssse3_x86_64.asm
114 VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_dct_ssse3_x86_64.asm
119 VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_dct_ssse3.c
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/
vp8_common.mk 104 VP8_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/sad_ssse3.asm
105 VP8_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/subpixel_ssse3.asm
106 VP8_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/variance_ssse3.c
107 VP8_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/variance_impl_ssse3.asm
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/
vp9_common.mk 78 VP9_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/vp9_subpixel_8t_ssse3.asm
79 VP9_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/vp9_subpixel_bilinear_ssse3.asm
81 VP9_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/vp9_subpixel_8t_intrin_ssse3.c
90 VP9_COMMON_SRCS-$(HAVE_SSSE3) += common/x86/vp9_intrapred_ssse3.asm
vp9cx.mk 113 VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_quantize_ssse3.asm
115 VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_sad_ssse3.asm
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/test/
intrapred_test.cc 292 #if HAVE_SSSE3
380 #if HAVE_SSSE3

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