| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) {
74 switch ((Imm >> 6) & 0x7) {
85 static inline unsigned getShiftValue(unsigned Imm) {
86 return Imm & 0x3f;
90 /// imm: 6-bit shift amount
97 /// {5-0} = imm
99 unsigned Imm) {
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
110 return (STEnc << 6) | (Imm & 0x3f)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
46 if (Imm == 0)
49 if (Imm.getBitWidth() <= 64) {
51 if (isInt<32>(Imm.getSExtValue()))
54 if (isUInt<32>(Imm.getZExtValue()))
57 if ((Imm.getZExtValue() & 0xffffffff) == 0)
67 const APInt &Imm, Type *Ty) {
90 if (Idx == 0 && Imm.getBitWidth() <= 64) {
95 if (isInt<16>(Imm.getSExtValue()))
100 if (Idx == 1 && Imm.getBitWidth() <= 64)
[all...] |
| SystemZTargetTransformInfo.h | 45 int getIntImmCost(const APInt &Imm, Type *Ty);
47 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
48 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize,
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize
[all...] |
| MipsISelDAGToDAG.h | 56 /// (reg + imm).
87 virtual bool selectVSplat(SDNode *N, APInt &Imm,
90 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
92 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
94 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
96 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
98 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
100 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
102 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
104 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const
[all...] |
| MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instruction sequence to load immediate Imm. The last
28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
36 /// load immediate Imm
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
40 /// load immediate Imm
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
44 /// load immediate Imm
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
47 /// GetInstSeqLs - Get instruction sequences to load immediate Imm.
48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs)
[all...] |
| MipsSEISelDAGToDAG.h | 81 bool selectVSplat(SDNode *N, APInt &Imm,
84 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
87 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
89 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
91 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
93 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
95 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
97 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
99 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
101 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override
[all...] |
| MipsISelDAGToDAG.cpp | 117 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
123 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
128 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
133 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
138 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
143 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
148 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
153 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
158 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
163 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const
[all...] |
| MipsSEISelDAGToDAG.cpp | 478 // Returns true and sets Imm if:
481 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
499 Imm = SplatValue;
507 // true and sets Imm if:
521 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
534 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
544 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
545 return selectVSplatCommon(N, Imm, false, 1);
549 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
550 return selectVSplatCommon(N, Imm, false, 2)
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
20 Target = Addr+Size+Imm;
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
55 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
63 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
84 void DecodeBLENDMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
86 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
[all...] |
| X86ShuffleDecode.cpp | 25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
33 unsigned ZMask = Imm & 15;
34 unsigned CountD = (Imm >> 4) & 3;
35 unsigned CountS = (Imm >> 6) & 3;
96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
105 if (i >= Imm) M = i - Imm + l;
110 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
118 unsigned Base = i + Imm;
125 void DecodePALIGNRMask(MVT VT, unsigned Imm,
[all...] |
| /external/llvm/test/MC/Mips/ |
| sym-expr.s | 11 jal __start + 0x4 # CHECK: instruction: [jal, Imm<__start+4>]
12 jal __start + (-0x10) # CHECK: instruction: [jal, Imm<__start-16>]
13 jal (__start + (-0x10)) # CHECK: instruction: [jal, Imm<__start-16>]
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonInstPrinter.cpp | 131 int64_t Imm;
132 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
133 Imm = SignExtend64<9>(Imm);
135 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO.");
136 O << formatImm(Imm/64);
141 int64_t Imm;
142 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm);
143 Imm = SignExtend64<10>(Imm);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 38 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
40 return BaseT::getIntImmCost(Imm, Ty);
48 if (Imm == 0)
51 if (Imm.getBitWidth() <= 64) {
52 if (isInt<16>(Imm.getSExtValue()))
55 if (isInt<32>(Imm.getSExtValue())) {
57 if ((Imm.getZExtValue() & 0xFFFF) == 0)
67 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
70 return BaseT::getIntImmCost(IID, Idx, Imm, Ty);
85 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 126 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) {
127 if (!isUInt<N>(Imm))
129 Inst.addOperand(MCOperand::createImm(Imm));
134 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) {
135 if (!isUInt<N>(Imm))
137 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
141 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm,
144 return decodeUImmOperand<4>(Inst, Imm);
147 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm,
149 return decodeUImmOperand<1>(Inst, Imm);
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyMCInstLower.cpp | 84 const ConstantFP *Imm = MO.getFPImm();
85 if (Imm->getType()->isFloatTy())
86 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
87 else if (Imm->getType()->isDoubleTy())
88 MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 83 uint16_t Imm = MI->getOperand(OpNo).getImm();
84 if (Imm != 0) {
232 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
233 int32_t SImm = static_cast<int32_t>(Imm);
239 if (Imm == FloatToBits(0.0f))
241 else if (Imm == FloatToBits(1.0f))
243 else if (Imm == FloatToBits(-1.0f))
245 else if (Imm == FloatToBits(0.5f))
247 else if (Imm == FloatToBits(-0.5f))
249 else if (Imm == FloatToBits(2.0f)
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 85 O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
95 int64_t Imm = MO.getImm();
99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
145 int64_t Imm = MO.getImm();
149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
219 int Imm = (int) MO.getImm();
221 if (Imm)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 89 static uint32_t getIntInlineImmEncoding(IntTy Imm) {
90 if (Imm >= 0 && Imm <= 64)
91 return 128 + Imm;
93 if (Imm >= -16 && Imm <= -1)
94 return 192 + std::abs(Imm);
212 int64_t Imm = 0;
215 Imm = Op.getImm();
220 OS.write((uint8_t) ((Imm >> (8 * j)) & 0xff))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.h | 46 int64_t Imm) const;
|
| SIInstrInfo.cpp | 53 int64_t Imm) const
57 MachineInstrBuilder(MI).addImm(Imm);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 195 const MCOperand &Imm, int AlignSize) {
198 if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
228 assert(Imm.isExpr() && "Expected expression and found none");
252 OutStreamer.EmitValue(Imm.getExpr(), AlignSize);
271 const MCOperand &Imm = MappedInst.getOperand(1);
274 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8);
292 MCOperand &Imm = MappedInst.getOperand(1);
294 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4);
367 int64_t Imm;
369 bool Success = Expr->evaluateAsAbsolute(Imm);
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfo.h | 298 bool isLegalAddImmediate(int64_t Imm) const;
304 bool isLegalICmpImmediate(int64_t Imm) const;
377 int getIntImmCost(const APInt &Imm, Type *Ty) const;
382 int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
384 int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
567 virtual bool isLegalAddImmediate(int64_t Imm) = 0;
568 virtual bool isLegalICmpImmediate(int64_t Imm) = 0;
591 virtual int getIntImmCost(const APInt &Imm, Type *Ty) = 0;
592 virtual int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
594 virtual int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
[all...] |
