| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | 29 #define OP2(a,b) {OPND(a), OPND(b)}
55 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
61 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
1240 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1242 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1246 {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1249 {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1252 {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
1254 {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1257 {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF}
[all...] |
| cr16-opc.c | 138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
144 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
152 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
154 {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
|
| /external/pcre/dist/ |
| pcre_jit_compile.c | 521 #define OP2(op, dst, dstw, src1, src1w, src2, src2w) \
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic6x-opcode-table.h | 43 #define OP2(a, b) 2, { a, b }
134 OP2(ORXREG1, OWREG1),
139 OP2(ORREGL1, OWREGL1),
144 OP2(ORXREG1, OWREG1),
150 OP2(ORREGD1, OWREGD12),
156 OP2(ORXREG1, OWREG1),
355 OP2(OLCST, OWREG1),
361 OP2(OACST, OWREG1),
513 OP2(OLCST, ORWREG1),
518 OP2(ORXREG1, OWREG2)
[all...] |
| h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
554 {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, MEMRELAX | DSTDISP32LIST, E}}}, \
558 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
559 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
560 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \
561 {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \
562 {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}}
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
572 {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, MEMRELAX | DISP32LIST, E}}}, \
576 {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}},
[all...] |
| sparc.h | 251 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
260 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
|
| /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/ |
| sm4_to_tgsi.cpp | 240 #define OP2(n) OP2_(n, n)
261 OP2(ADD);
262 OP2(MUL);
264 OP2(DIV);
267 OP2(MIN);
268 OP2(MAX);
276 OP2(AND);
277 OP2(OR);
278 OP2(XOR);
281 OP2(DP2)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600Defines.h | 42 OP2 = (1 << 11),
|
| R600InstrInfo.cpp | 141 (TargetFlags & R600_InstFlag::OP2) |
[all...] |
| /development/ndk/platforms/android-21/arch-arm64/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/current/platforms/android-21/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/current/platforms/android-23/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/current/platforms/android-24/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /bionic/libc/kernel/uapi/asm-arm64/asm/ |
| kvm.h | 136 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /external/kernel-headers/original/uapi/asm-arm64/asm/ |
| kvm.h | 181 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
187 ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 136 Desc.TSFlags & R600_InstFlag::OP2)) {
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 299 LCLS OP2
302 OP2 SETS "ORR"
305 OP2 SETS "AND"
318 $OP2 $lsb2, $lsb2, $lsb0 ;// e2 = e2 | e0
|
| /external/boringssl/src/decrepit/cast/ |
| cast.c | 90 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \
99 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-rx.c | [all...] |
