| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 105 MachineOperand &Op4 = MI->getOperand(4);
114 NewMI->addOperand(Op4);
147 MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
151 Hexagon::C6)->addOperand(Op4);
189 MachineOperand &Op4 = MI->getOperand(4); // Modifier value.
192 Hexagon::C6)->addOperand(Op4);
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/detail/ |
| reduce.hpp | 157 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
162 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
182 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 648 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
653 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
657 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
682 unsigned Op1, Op2, Op3, Op4, Op5;
687 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
692 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
703 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
708 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
711 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
722 unsigned Op4 = fieldFromInstruction(Insn, 16, 4)
[all...] |
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/ |
| reduce.hpp | 71 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
75 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
80 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/detail/ |
| reduce.hpp | 168 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
173 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
182 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
|
| /external/opencv3/modules/cudaarithm/src/cuda/ |
| minmax_mat.cu | 114 template <class Op4>
123 gridTransformBinary(src1_, src2_, dst_, Op4(), stream);
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
| reduce.hpp | 186 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
191 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
207 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
211 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/ |
| reduce.hpp | 66 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
70 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
75 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/ |
| reduce.hpp | 69 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
73 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
78 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | [all...] |
