| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 209 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) {
210 if (isa<SelectInst>(Inst) && OpIdx == 0)
314 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx;
315 ++OpIdx) {
316 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n');
317 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() ||
318 !shouldSExtOperand(Inst, OpIdx)) {
323 Value *Opnd = Inst->getOperand(OpIdx);
326 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType()
[all...] |
| AArch64PromoteConstant.cpp | 234 /// Check if the given use (Instruction + OpIdx) of Cst should be converted into
240 unsigned OpIdx) {
243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2)
247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0)
251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1)
254 if (isa<const AllocaInst>(Instr) && OpIdx > 0)
258 if (isa<const LoadInst>(Instr) && OpIdx > 0)
262 if (isa<const StoreInst>(Instr) && OpIdx > 1)
266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0)
432 DEBUG(dbgs() << "Considered use, opidx " << Use.getOperandNo() << ":\n")
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeEmitterGen.cpp | 87 unsigned OpIdx;
88 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
90 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
91 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
114 OpIdx = NumberedOp++;
117 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
128 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
134 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
193 unsigned OpIdx;
[all...] |
| CodeGenInstruction.cpp | 137 unsigned OpIdx;
138 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
144 /// given name. If so, return true and set OpIdx to the index of the
146 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
150 OpIdx = i;
173 unsigned OpIdx = getOperandNamed(OpName);
177 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
183 return std::make_pair(OpIdx, 0U);
187 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 388 unsigned OpIdx = 0;
390 bool DstIsDead = MI.getOperand(OpIdx).isDead();
391 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
403 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
417 SrcOpIdx = OpIdx++;
420 MIB.addOperand(MI.getOperand(OpIdx++));
421 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | [all...] |
| ExecutionDepsFix.cpp | 201 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
473 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
475 unsigned reg = MI->getOperand(OpIdx).getReg();
559 unsigned OpIdx = UndefReads.back().second;
566 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
567 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
574 OpIdx = UndefReads.back().second;
|
| TargetInstrInfo.cpp | 677 unsigned OpIdx[4][4] = {
693 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
694 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
695 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
696 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
[all...] |
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.h | 42 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| ScheduleDAGInstrs.h | 56 /// For non-data-dependent uses, OpIdx == -1.
59 int OpIdx;
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
|
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 170 for (unsigned OpIdx = 0, OpIdxEnd = Inst.getNumOperands(); OpIdx != OpIdxEnd;
171 ++OpIdx)
172 Latency = std::max(Latency, IID.getOperandCycle(SCClass, OpIdx));
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 63 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
234 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
236 const MCOperand &MO = MI.getOperand(OpIdx);
271 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
272 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
281 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 61 int OpIdx = TII->getOperandIdx(*OldMI, Op);
62 if (OpIdx > -1) {
63 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
|
| AMDGPUOpenCLImageTypeLoweringPass.cpp | 121 GetArgMD(MDNode *KernelMDNode, unsigned OpIdx) {
125 Res.push_back(Node->getOperand(OpIdx));
|
| SIInstrInfo.h | 377 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
379 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
381 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 98 unsigned OpIdx, SDep& dep) const;
|
| ScheduleDAGSDNodes.cpp | 626 unsigned OpIdx, SDep& dep) const{
634 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
638 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.h | 93 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.h | 43 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.h | 40 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
178 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
|
| /external/llvm/include/llvm/IR/ |
| InstrTypes.h | [all...] |
| /external/llvm/lib/ExecutionEngine/RuntimeDyld/ |
| RuntimeDyldChecker.cpp | 254 unsigned OpIdx = OpIdxExpr.getValue();
255 if (OpIdx >= Inst.getNumOperands()) {
258 ErrMsgStream << "Invalid operand index '" << format("%i", OpIdx)
267 const MCOperand &Op = Inst.getOperand(OpIdx);
271 ErrMsgStream << "Operand '" << format("%i", OpIdx) << "' of instruction '"
[all...] |
