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    Searched refs:RegionEnd (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/Target/AMDGPU/
R600Packetizer.cpp 372 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
373 RegionEnd != MBB->begin();) {
376 MachineBasicBlock::iterator I = RegionEnd;
384 if (I == RegionEnd) {
385 RegionEnd = std::prev(RegionEnd);
390 if (I == std::prev(RegionEnd)) {
391 RegionEnd = std::prev(RegionEnd);
395 Packetizer.PacketizeMIs(&*MBB, &*I, RegionEnd);
    [all...]
  /external/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 121 MachineBasicBlock::iterator RegionEnd;
123 /// Instructions in this region (distance(RegionBegin, RegionEnd)).
189 MachineBasicBlock::iterator end() const { return RegionEnd; }
  /external/llvm/lib/CodeGen/
PostRASchedulerList.cpp 131 /// The index in BB of RegionEnd.
151 // Set the index of RegionEnd within the current BB.
384 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd,
654 RegionBegin = RegionEnd;
658 BB->splice(RegionEnd, BB, FirstDbgValue);
663 BB->splice(RegionEnd, BB, SU->getInstr());
666 TII->insertNoop(*BB, RegionEnd);
671 RegionBegin = std::prev(RegionEnd);
MachineScheduler.cpp 312 /// scheduler must update the RegionBegin and RegionEnd positions cached by
417 // Break the block into scheduling regions [I, RegionEnd), and schedule each
418 // region as soon as it is discovered. RegionEnd points the scheduling
419 // boundary at the bottom of the region. The DAG does not include RegionEnd,
420 // but the region does (i.e. the next RegionEnd is above the previous
421 // RegionBegin). If the current block has no terminator then RegionEnd ==
426 // 'RegionEnd' are invalid across these calls.
431 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
432 RegionEnd != MBB->begin(); RegionEnd = Scheduler.begin())
    [all...]
ScheduleDAGInstrs.cpp 195 RegionEnd = end;
214 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
755 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) {
    [all...]

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