/external/llvm/include/llvm/CodeGen/ |
ScheduleDAG.h | 43 /// SDep - Scheduling dependency. This represents one direction of an 45 class SDep { 95 /// SDep - Construct a null SDep. This is only for use by container 97 /// have null SDep edges. 98 SDep() : Dep(nullptr, Data) {} 100 /// SDep - Construct an SDep with the specified values. 101 SDep(SUnit *S, Kind kind, unsigned Reg) 109 "SDep::Anti and SDep::Output must use a non-zero Reg!") [all...] |
MachineScheduler.h | 295 bool addEdge(SUnit *SuccSU, const SDep &PredDep); 348 void releaseSucc(SUnit *SU, SDep *SuccEdge); 350 void releasePred(SUnit *SU, SDep *PredEdge);
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/external/llvm/lib/CodeGen/ |
ScheduleDAG.cpp | 65 bool SUnit::addPred(const SDep &D, bool Required) { 67 for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end(); 78 SDep ForwardD = *I; 80 for (SmallVectorImpl<SDep>::iterator II = PredSU->Succs.begin(), 93 SDep P = D; 97 if (D.getKind() == SDep::Data) { 133 void SUnit::removePred(const SDep &D) { 135 for (SmallVectorImpl<SDep>::iterator I = Preds.begin(), E = Preds.end(); 139 SDep P = D; 142 SmallVectorImpl<SDep>::iterator Succ = std::find(N->Succs.begin() [all...] |
ScheduleDAGInstrs.cpp | 267 SDep Dep; 269 Dep = SDep(SU, SDep::Artificial); 274 Dep = SDep(SU, SDep::Data, *Alias); 300 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; 310 (Kind != SDep::Output || !MO.isDead() || 312 if (Kind == SDep::Anti [all...] |
AggressiveAntiDepBreaker.cpp | 253 static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) { 257 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) { 267 const SDep *Next = nullptr; 279 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 811 std::vector<const SDep *> Edges; 830 const SDep *Edge = Edges[i]; 833 if ((Edge->getKind() != SDep::Anti) && 834 (Edge->getKind() != SDep::Output)) continue; 876 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) [all...] |
CriticalAntiDepBreaker.cpp | 129 static const SDep *CriticalPathStep(const SUnit *SU) { 130 const SDep *Next = nullptr; 141 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 539 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) { 543 if (Edge->getKind() == SDep::Anti) { 565 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 566 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
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MachineScheduler.cpp | 525 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) { 542 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { 581 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { [all...] |
PostRASchedulerList.cpp | 179 void ReleaseSucc(SUnit *SU, SDep *SuccEdge); 438 void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGFast.cpp | 88 void AddPred(SUnit *SU, const SDep &D) { 94 void RemovePred(SUnit *SU, const SDep &D) { 99 void ReleasePred(SUnit *SU, SDep *PredEdge); 140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { 280 SDep ChainPred; 281 SmallVector<SDep, 4> ChainSuccs; 282 SmallVector<SDep, 4> LoadPreds; 283 SmallVector<SDep, 4> NodePreds; 284 SmallVector<SDep, 4> NodeSuccs; 309 const SDep &Pred = LoadPreds[i] [all...] |
ScheduleDAGVLIW.cpp | 87 void releaseSucc(SUnit *SU, const SDep &D); 116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
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ScheduleDAGRRList.cpp | 199 void AddPred(SUnit *SU, const SDep &D) { 207 void RemovePred(SUnit *SU, const SDep &D) { 218 void ReleasePred(SUnit *SU, const SDep *PredEdge); 225 void CapturePred(SDep *PredEdge); 365 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { 791 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { [all...] |
ScheduleDAGSDNodes.h | 32 /// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output 98 unsigned OpIdx, SDep& dep) const;
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ScheduleDAGSDNodes.cpp | 486 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier) 487 : SDep(OpSU, SDep::Data, PhysReg); 626 unsigned OpIdx, SDep& dep) const{ 631 if (dep.getKind() != SDep::Data) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonVLIWPacketizer.h | 75 bool isCallDependent(const MachineInstr* MI, SDep::Kind DepType, 77 bool promoteToDotCur(MachineInstr* MI, SDep::Kind DepType, 85 bool promoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
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HexagonVLIWPacketizer.cpp | 266 SDep::Kind DepType, unsigned DepReg) { 281 if (HII->isIndirectCall(MI) && (DepType == SDep::Data)) { 290 static bool isRegDependence(const SDep::Kind DepType) { 291 return DepType == SDep::Data || DepType == SDep::Anti || 292 DepType == SDep::Output; 333 SDep::Kind DepType, MachineBasicBlock::iterator &MII, 335 assert(DepType == SDep::Data); 413 SDep::Kind DepType, MachineBasicBlock::iterator &MII, 415 assert (DepType == SDep::Data) [all...] |
HexagonMachineScheduler.cpp | 34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
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/external/llvm/include/llvm/Target/ |
TargetSubtargetInfo.h | 27 class SDep; 152 virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
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/external/llvm/lib/Target/AMDGPU/ |
R600Packetizer.cpp | 201 const SDep &Dep = SUJ->Succs[i]; 204 if (Dep.getKind() == SDep::Anti) 206 if (Dep.getKind() == SDep::Output)
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