| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.h | 155 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
159 return get(Opcode).TSFlags & SIInstrFlags::SALU;
163 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
167 return get(Opcode).TSFlags & SIInstrFlags::VALU;
171 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
175 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
179 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
183 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
187 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
191 return get(Opcode).TSFlags & SIInstrFlags::SOPC
[all...] |
| R600Defines.h | 62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
|
| SIInsertWaits.cpp | 146 uint64_t TSFlags = MI.getDesc().TSFlags;
149 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
152 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
156 if (TSFlags & SIInstrFlags::LGKM_CNT) {
|
| R600OptimizeVectorRegisters.cpp | 134 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
250 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
330 if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
|
| AMDGPUInstrInfo.cpp | 257 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
261 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
|
| R600InstrInfo.cpp | 39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
43 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
132 unsigned TargetFlags = get(Opcode).TSFlags;
138 unsigned TargetFlags = get(Opcode).TSFlags;
146 unsigned TargetFlags = get(Opcode).TSFlags;
198 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 148 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
156 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
163 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
185 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
186 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
190 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
209 /// in an instruction with the specified TSFlags.
210 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
211 unsigned Size = X86II::getSizeOfImm(TSFlags);
212 bool isPCRel = X86II::isImmPCRel(TSFlags);
[all...] |
| X86BaseInfo.h | 565 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
566 return TSFlags >> X86II::OpcodeShift;
569 inline bool hasImm(uint64_t TSFlags) {
570 return (TSFlags & X86II::ImmMask) != 0;
573 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
575 inline unsigned getSizeOfImm(uint64_t TSFlags) {
576 switch (TSFlags & X86II::ImmMask) {
590 /// TSFlags indicates that it is pc relative.
591 inline unsigned isImmPCRel(uint64_t TSFlags) {
592 switch (TSFlags & X86II::ImmMask)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXReplaceImageHandles.cpp | 83 if (MCID.TSFlags & NVPTXII::IsTexFlag) {
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) {
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) {
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1);
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) {
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
|
| NVPTXInstrInfo.cpp | 69 // Look for the appropriate part of TSFlags
72 unsigned TSFlags =
73 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
74 isMove = (TSFlags == 1);
93 unsigned TSFlags =
94 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
95 isLoad = (TSFlags == 1);
104 unsigned TSFlags =
105 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
106 isStore = (TSFlags == 1)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
55 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
|
| MLxExpansionPass.cpp | 188 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
352 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
|
| ARMBaseRegisterInfo.cpp | 424 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
613 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
728 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
729 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCInstrInfo.cpp | 169 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
177 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
184 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
195 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
213 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
219 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
227 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
242 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
260 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
266 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 135 ((Desc.TSFlags & R600_InstFlag::OP1) ||
136 Desc.TSFlags & R600_InstFlag::OP2)) {
170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 287 uint64_t TSFlags = MCID.TSFlags;
289 isFirst = TSFlags & PPCII::PPC970_First;
290 isSingle = TSFlags & PPCII::PPC970_Single;
291 isCracked = TSFlags & PPCII::PPC970_Cracked;
292 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 43 uint64_t TSFlags = Desc.TSFlags;
50 if (TSFlags & X86II::LOCK)
|
| X86IntelInstPrinter.cpp | 39 uint64_t TSFlags = Desc.TSFlags;
41 if (TSFlags & X86II::LOCK)
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.cpp | 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
45 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
485 return GET_FLAG_OPERAND_IDX(get(MI.getOpcode()).TSFlags) != 0;
490 unsigned FlagIndex = GET_FLAG_OPERAND_IDX(get(MI->getOpcode()).TSFlags);
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 126 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, MI.getOpcode()) +
249 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, Opcode);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 244 unsigned MIFlags = Desc.TSFlags;
250 unsigned CompareFlags = Compare->getDesc().TSFlags;
266 unsigned Flags = MI->getDesc().TSFlags;
|
| SystemZRegisterInfo.cpp | 105 if (MI->getDesc().TSFlags & SystemZII::HasIndex
|
| SystemZInstrInfo.cpp | 202 if ((MCID.TSFlags & Flag) &&
494 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
625 return ((MCID.TSFlags & Flag) &&
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 146 uint64_t TSFlags; // Target Specific Flag values
|
