| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| relax.s | 27 bltzl $4, bar
55 bltzl $4, foo
|
| micromips-branch-relax.s | 149 bltzl $3, test3
|
| relax-at.d | 144 00000190 <foo\+0x190> bltzl a0,000001a0 <foo\+0x1a0>
184 00000210 <foo\+0x210> bltzl v0,00000220 <foo\+0x220>
337 000203e0 <bar\+0x190> bltzl a0,000203f0 <bar\+0x1a0>
377 00020460 <bar\+0x210> bltzl v0,00020470 <bar\+0x220>
|
| relax.d | 143 00000190 <foo\+0x190> bltzl a0,000001a0 <foo\+0x1a0>
183 00000210 <foo\+0x210> bltzl v0,00000220 <foo\+0x220>
336 000203e0 <bar\+0x190> bltzl a0,000203f0 <bar\+0x1a0>
376 00020460 <bar\+0x210> bltzl v0,00020470 <bar\+0x220>
|
| r6-removed.l | 30 .*:31: Error: opcode not supported on this processor: .* \(.*\) `bltzl \$28,1f'
|
| /external/valgrind/none/tests/mips32/ |
| branches.stdout.exp | 348 BLTZL
349 bltzl :: 9, RSval: 0
350 bltzl :: 10, RSval: 1
351 bltzl :: 3, RSval: -1
352 bltzl :: 4, RSval: -1
353 bltzl :: 5, RSval: -2
354 bltzl :: 6, RSval: -1
355 bltzl :: 15, RSval: 5
356 bltzl :: 8, RSval: -3
357 bltzl :: 17, RSval: 12
[all...] |
| /external/llvm/test/MC/Mips/ |
| mips-jump-delay-slots.s | 89 # CHECK: bltzl $6, 1332
91 bltzl $6,1332
|
| /external/valgrind/none/tests/mips64/ |
| branches.stdout.exp | 365 --- BLTZL --- if RSval < 0 then out = RDval + 4 else out = RDval + 6
366 bltzl :: out: 6, RDval: 0, RSval: 0
367 bltzl :: out: 7, RDval: 1, RSval: 1
368 bltzl :: out: 6, RDval: 2, RSval: -1
369 bltzl :: out: 7, RDval: 3, RSval: -1
370 bltzl :: out: 8, RDval: 4, RSval: -2
371 bltzl :: out: 9, RDval: 5, RSval: -1
372 bltzl :: out: 12, RDval: 6, RSval: 5
373 bltzl :: out: 11, RDval: 7, RSval: -3
374 bltzl :: out: 14, RDval: 8, RSval: 12
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/iq2000/ |
| allinsn.s | 190 .global bltzl
191 bltzl: label
192 bltzl %0,footext
|
| allinsn.d | 147 000000b8 <bltzl>:
148 b8: 04 02 ff d1 bltzl r0,0 <add>
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips2.s | 18 bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips2.s | 22 bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips2.s | 18 bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 37 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 37 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 41 bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
|
