| /art/runtime/arch/mips64/ |
| asm_support_mips64.S | 88 .macro MINint dreg,rreg,sreg,creg
91 .ifc \dreg, \rreg
92 selnez \dreg, \rreg, \creg
95 seleqz \dreg, \sreg, \creg
98 or \dreg, \dreg, \creg
103 .macro MINs dreg,rreg,sreg
107 MINint \dreg, \rreg, \sreg, $at
112 .macro MINu dreg,rreg,sreg
116 MINint \dreg, \rreg, \sreg, $a
[all...] |
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 134 .macro MINint dreg,rreg,sreg,creg
138 .ifc \dreg, \rreg
139 selnez \dreg, \rreg, \creg
142 seleqz \dreg, \sreg, \creg
145 or \dreg, \dreg, \creg
147 movn \dreg, \rreg, \creg
148 movz \dreg, \sreg, \creg
154 .macro MINs dreg,rreg,sreg
158 MINint \dreg, \rreg, \sreg, $a
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| am33-2.c | 89 dreg (func_arg *arg, insn_data *data) function
90 #define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } } macro
358 lparen, amreg (4), rparen, comma, dreg (0, 8), tick_random);
360 lparen, amreg (4), plus, rparen, comma, dreg (0, 8), tick_random);
362 lparen, spreg, rparen, comma, dreg (0, 8));
364 dreg (4, 9), comma, lparen, amreg (0), rparen, tick_random);
366 dreg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random);
368 dreg (4, 9), comma, lparen, spreg, rparen);
370 dreg (4, 9), comma, dreg (0, 8), tick_random)
[all...] |
| /system/core/libpixelflinger/arch-mips64/ |
| col32cb16blend.S | 17 .macro pixel dreg src f sR sG sB shift
48 addu \dreg,$t2,\sB
51 or \dreg,\dreg,$t0
52 or \dreg,\dreg,$t1
|
| t32cb16blend.S | 24 * blend one of 2 16bpp RGB pixels held in dreg selected by shift
27 * Assumes that the dreg data is little endian and that
34 .macro pixel dreg src fb shift
46 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
48 ext $a4,\dreg,\shift+5,6 # start green extraction dst[\shift:10..5]
61 ext $a4,\dreg,\shift,5 # start blue extraction dst[\shift:4..0]
|
| /system/core/libpixelflinger/arch-mips/ |
| col32cb16blend.S | 17 .macro pixel dreg src f sR sG sB shift
53 addu \dreg,$t6,\sB
56 or \dreg,\dreg,$t4
57 or \dreg,\dreg,$t5
58 andi \dreg, 0xffff
|
| t32cb16blend.S | 25 * blend one of 2 16bpp RGB pixels held in dreg selected by shift
28 * Assumes that the dreg data is little endian and that
36 .macro pixel dreg src fb shift
52 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
54 ext $t0,\dreg,\shift+5,6 # start green extraction dst[\shift:10..5]
67 ext $t0,\dreg,\shift,5 # start blue extraction dst[\shift:4..0]
94 .macro pixel dreg src fb shift
119 srl $t8,\dreg,\shift+6+5
141 srl $t8,\dreg,\shift+5
153 srl $t8,\dreg,\shif
[all...] |
| /external/v8/src/ppc/ |
| simulator-ppc.h | 186 void set_d_register_from_double(int dreg, const double dbl) {
187 DCHECK(dreg >= 0 && dreg < kNumFPRs);
188 *bit_cast<double*>(&fp_registers_[dreg]) = dbl;
190 double get_double_from_d_register(int dreg) {
191 DCHECK(dreg >= 0 && dreg < kNumFPRs);
192 return *bit_cast<double*>(&fp_registers_[dreg]);
194 void set_d_register(int dreg, int64_t value) {
195 DCHECK(dreg >= 0 && dreg < kNumFPRs)
[all...] |
| deoptimizer-ppc.cc | 163 const DoubleRegister dreg = DoubleRegister::from_code(code); local
165 __ stfd(dreg, MemOperand(sp, offset));
301 const DoubleRegister dreg = DoubleRegister::from_code(code); local
303 __ lfd(dreg, MemOperand(r4, src_offset));
|
| /external/vixl/examples/ |
| add3-double.cc | 69 printf("%f + %f + %f = %f\n", a, b, c, simulator.dreg(0));
|
| add4-double.cc | 79 printf("%ld + %f + %ld + %f = %f\n", a, b, c, d, simulator.dreg(0));
|
| /external/v8/src/arm/ |
| simulator-arm.h | 147 void set_dw_register(int dreg, const int* dbl);
150 void get_d_register(int dreg, uint64_t* value);
151 void set_d_register(int dreg, const uint64_t* value);
152 void get_d_register(int dreg, uint32_t* value);
153 void set_d_register(int dreg, const uint32_t* value);
162 void set_d_register_from_double(int dreg, const double& dbl) {
163 SetVFPRegister<double, 2>(dreg, dbl);
166 double get_double_from_d_register(int dreg) {
167 return GetFromVFPRegister<double, 2>(dreg);
|
| simulator-arm.cc | 929 void Simulator::set_dw_register(int dreg, const int* dbl) {
930 DCHECK((dreg >= 0) && (dreg < num_d_registers));
931 registers_[dreg] = dbl[0];
932 registers_[dreg + 1] = dbl[1];
936 void Simulator::get_d_register(int dreg, uint64_t* value) {
937 DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
938 memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value));
942 void Simulator::set_d_register(int dreg, const uint64_t* value)
[all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.cc | 175 return dreg(0);
639 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1));
640 int64_t result = target(dreg(0), dreg(1));
654 TraceSim("Argument: %f\n", dreg(0));
655 double result = target(dreg(0));
669 TraceSim("Arguments: %f, %f\n", dreg(0), dreg(1));
670 double result = target(dreg(0), dreg(1))
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm_toIR.c | 693 /* Plain ("low level") read from a VFP Dreg. */
700 /* Architected read from a VFP Dreg. */
705 /* Plain ("low level") write to a VFP Dreg. */
713 /* Architected write to a VFP Dreg. Handles conditional writes to the
736 /* Plain ("low level") read from a Neon Integer Dreg. */
743 /* Architected read from a Neon Integer Dreg. */
748 /* Plain ("low level") write to a Neon Integer Dreg. */
756 /* Architected write to a Neon Integer Dreg. Handles conditional
2859 UInt dreg = get_neon_d_regno(theInstr); local
2908 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
2988 UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); local
3042 UInt dreg = get_neon_d_regno(theInstr); local
4834 UInt dreg = get_neon_d_regno(theInstr); local
5247 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
5913 UInt dreg = get_neon_d_regno(theInstr); local
6628 UInt dreg = get_neon_d_regno(theInstr); local
7648 UInt dreg = get_neon_d_regno(theInstr); local
[all...] |
| /art/runtime/interpreter/mterp/arm/ |
| header.S | 168 .macro PREFETCH_ADVANCE_INST dreg, sreg, count
169 ldrh \dreg, [\sreg, #((\count)*2)]!
|
| /art/runtime/interpreter/mterp/arm64/ |
| header.S | 165 .macro PREFETCH_ADVANCE_INST dreg, sreg, count
166 ldrh \dreg, [\sreg, #((\count)*2)]!
|
| /external/vixl/src/vixl/a64/ |
| simulator-a64.cc | [all...] |
| /external/v8/test/cctest/ |
| test-utils-arm64.h | 89 inline double dreg(unsigned code) const { function in class:RegisterDump
|
| /external/vixl/test/ |
| test-utils-a64.h | 110 inline double dreg(unsigned code) const { function in class:vixl::RegisterDump
|
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 220 Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0); local
226 EXPECT_TRUE(reg.Overlaps(dreg));
232 dreg = Arm64ManagedRegister::FromDRegister(D5);
238 EXPECT_TRUE(reg.Overlaps(dreg));
244 dreg = Arm64ManagedRegister::FromDRegister(D7);
250 EXPECT_TRUE(reg.Overlaps(dreg));
256 dreg = Arm64ManagedRegister::FromDRegister(D31);
262 EXPECT_TRUE(reg.Overlaps(dreg));
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| msp430-decode.opc | 359 opcode:4 sreg:4 Ad:1 BW:1 As:2 Dreg:4
370 /** dopc sreg a b as dreg %D%b %1,%0 */
372 ID (dopc_to_id (dopc)); ASX (sreg, as, srxt_bits); ADX (dreg, a, dsxt_bits); ABW (al_bit, b);
393 /** 0001 00so c b ad dreg %S%b %1 */
395 ID (sopc_to_id (so,c)); ASX (dreg, ad, srxt_bits); ABW (al_bit, b);
|
| /art/runtime/interpreter/mterp/mips/ |
| header.S | 257 #define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255
|
| /external/vixl/test/examples/ |
| test-examples.cc | 334 assert(regs.dreg(0) == Add3DoubleC(A, B, C)); \
360 assert(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Blur.S | 115 .macro vertfetch_noclamp i, dreg
121 umlal v12.4s, v16.4h, \dreg
122 umlal2 v13.4s, v16.8h, \dreg
124 umlal v14.4s, v11.4h, \dreg
126 umlal2 v15.4s, v11.8h, \dreg
137 .macro vertfetch_clamped i, dreg
147 umlal v12.4s, v16.4h, \dreg
148 umlal2 v13.4s, v16.8h, \dreg
150 umlal v14.4s, v11.4h, \dreg
152 umlal2 v15.4s, v11.8h, \dreg
[all...] |
