| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags;
195 assert(!isReg() && "Register operands can't have target flags");
200 assert(!isReg() && "Register operands can't have target flags");
229 /// isReg - Tests if this is a MO_Register operand.
230 bool isReg() const { return OpKind == MO_Register; }
268 assert(isReg() && "This is not a register operand!");
273 assert(isReg() && "Wrong MachineOperand accessor");
278 assert(isReg() && "Wrong MachineOperand accessor");
283 assert(isReg() && "Wrong MachineOperand accessor");
288 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
192 if (Op.isReg()) {
299 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
301 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
304 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
307 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
310 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
313 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
|
| /external/llvm/lib/MC/ |
| MCInstrDesc.cpp | 47 if (MI.getOperand(i).isReg() &&
66 if (MI.getOperand(i).isReg() &&
|
| MCInst.cpp | 22 else if (isReg())
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 67 assert(FoldOp->isReg());
111 assert(Old.isReg());
183 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
184 !MI->getOperand(CommuteIdx1).isReg()))
208 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
327 if (!FoldingImm && !OpToFold.isReg())
338 if (OpToFold.isReg() &&
368 assert(Fold.OpToFold && Fold.OpToFold->isReg());
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
220 assert(MI.getOperand(OpNo+1).isReg());
239 assert(MI.getOperand(OpNo+1).isReg());
259 assert(MI.getOperand(OpNo+1).isReg());
275 assert(MI.getOperand(OpNo+1).isReg());
291 assert(MI.getOperand(OpNo+1).isReg());
[all...] |
| /sdk/find_java2/FindJava2/ |
| FindJava2.cpp | 120 bool isReg = (p == javaPath);
121 if (isReg) {
124 _tprintf(_T("%c [%s] %s\n"), isReg ? '*' : ' ', p.getVersion(), p.mPath);
|
| /external/llvm/include/llvm/MC/MCParser/ |
| MCParsedAsmOperand.h | 58 /// isReg - Is this a register operand?
59 virtual bool isReg() const = 0;
|
| /external/llvm/include/llvm/MC/ |
| MachineLocation.h | 53 bool isReg() const { return IsRegister; }
|
| MCInst.h | 56 bool isReg() const { return Kind == kRegister; }
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
|
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 60 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
|
| LivePhysRegs.cpp | 47 if (O->isReg()) {
60 if (!O->isReg() || !O->readsReg() || O->isUndef())
77 if (O->isReg()) {
98 if (Reg.second->isReg() && Reg.second->isDead())
|
| MachineInstr.cpp | 99 assert(isReg() && "Wrong MachineOperand accessor");
119 if (!isReg() || !isOnRegUseList())
134 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
143 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
152 assert((!isReg() || !isTied()) &&
164 assert((!isReg() || !isTied()) &&
186 bool WasReg = isReg();
698 if (MO.isReg())
707 if (MO.isReg())
754 bool isImpReg = Op.isReg() && Op.isImplicit()
[all...] |
| DeadMachineInstructionElim.cpp | 74 if (MO.isReg() && MO.isDef()) {
140 if (MO.isReg() && MO.isDef()) {
159 if (MO.isReg() && MO.isUse()) {
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 62 if (!MI->getOperand(0).isReg())
86 || (!MI->getOperand(0).isReg())
112 if (MO.isReg()) {
139 if (MO.isReg() && MO.getReg() == SP::G0)
|
| /external/llvm/lib/Target/BPF/InstPrinter/ |
| BPFInstPrinter.cpp | 56 if (Op.isReg()) {
77 assert(RegOp.isReg() && "Register operand not a register");
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCCodeEmitter.cpp | 119 if (MO.isReg())
146 if (MO.isReg() || MO.isImm())
181 if (MO.isReg() || MO.isImm())
194 if (MO.isReg() || MO.isImm())
206 if (MO.isReg() || MO.isImm())
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegStackify.cpp | 90 if (!MO.isReg())
153 if (!Op.isReg() || Op.isImplicit() || !Op.isUse())
238 if (!MO.isReg())
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 67 if (MO.isReg() && MO.isDef())
93 if (MO.isReg() && MO.isDead() && MO.isDef()) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 152 if (II->getOperand(i).isReg() &&
506 MI->getOperand(0).isReg() &&
514 isSecondOpReg = MI->getOperand(2).isReg();
548 if (MI->getOperand(0).isReg() &&
605 if (MO.isReg() && MO.isUse()) {
612 if (localMO.isReg() && localMO.isUse() &&
667 if (cmpInstr->getOperand(0).isReg() &&
670 if (cmpInstr->getOperand(1).isReg() &&
|
| HexagonExpandCondsets.cpp | 277 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
309 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
337 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
366 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
437 if (Op.isReg() && Op.isDef())
514 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef())
553 if (!Op.isReg() || !Op.isDef())
631 if (!Op.isReg() || !Op.isUse())
652 if (SO.isReg()) {
758 if (!Op.isReg() || !Op.isDef()
[all...] |
| HexagonVLIWPacketizer.cpp | 115 if (!MO.isReg() || !MO.isDef())
283 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg))
351 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
391 if (MO.isReg() && MO.getReg() == DestReg)
457 if (MO.isReg() && MO.isDef())
461 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
467 assert(Op1.isReg() && "Post increment operand has be to a register.");
473 assert(Op0.isReg() && "Post increment operand has be to a register.");
532 if (Val.isReg() && Val.getReg() != DepReg)
585 if (!MO.isReg())
[all...] |
| HexagonHardwareLoops.cpp | 312 bool isReg() const { return Kind == CV_Register; }
316 assert(isReg() && "Wrong CountValue accessor");
320 assert(isReg() && "Wrong CountValue accessor");
329 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
642 if (Op1.isReg()) {
662 if (InitialValue->isReg()) {
669 if (EndValue->isReg()) {
696 if (Start->isReg()) {
702 if (End->isReg()) {
709 if (!Start->isReg() && !Start->isImm()
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 85 if (Op.isReg() && TargetRegisterInfo::isVirtualRegister(Op.getReg())) {
98 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
|
