| /art/runtime/interpreter/mterp/arm/ |
| op_goto_32.S | 15 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa
|
| binopWide2addr.S | 24 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
|
| binopWide.S | 28 orrs ip, r2, r3 @ second arg (r2-r3) is zero?
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| tcompat2.d | 19 0+10 <[^>]*> 4308 * orrs r0, r1
20 0+12 <[^>]*> 4308 * orrs r0, r1
|
| armv1.s | 21 orrs r0, r0, r0
|
| thumb2_it.s | 23 orrs r0, r0, r2
|
| thumb2_it.d | 26 0+02c <[^>]+> 4310 orrs r0, r2
|
| thumb2_it_auto.d | 26 0+02c <[^>]+> 4310 orrs r0, r2
|
| armv1.d | 28 0+44 <[^>]*> e1900000 ? orrs r0, r0, r0
|
| thumb-eabi.d | 38 0+038 <[^>]+> 4318 orrs r0, r3
|
| thumb.d | 39 0+038 <[^>]+> 4318 orrs r0, r3
|
| thumb32.d | 169 0[0-9a-f]+ <[^>]+> 4300 orrs r0, r0
170 0[0-9a-f]+ <[^>]+> 4305 orrs r5, r0
171 0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
172 0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
173 0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5
179 0[0-9a-f]+ <[^>]+> ea50 0000 orrs\.w r0, r0, r0
[all...] |
| thumb32.s | 153 arit3 orr orrs orr.w orrs.w
|
| /external/compiler-rt/lib/builtins/arm/ |
| comparesf2.S | 55 orrs r12, r2, r3, lsr #1
76 // still clear from the shift argument in orrs; if a is positive and b
116 orrs r12, r2, r3, lsr #1
|
| /external/llvm/test/MC/ARM/ |
| thumb_rewrites.s | 92 orrs r0, r0, r1
93 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
95 orrs r0, r1, r0
96 @ CHECK: orrs r0, r1 @ encoding: [0x08,0x43]
|
| basic-thumb-instructions.s | 450 orrs r3, r4
452 @ CHECK-ERRORS: orrs r3, r4 @ encoding: [0x23,0x43]
|
| /system/core/libpixelflinger/ |
| t32cb16blend.S | 169 orrs r3, r4, r5
188 orrs r3, r4, r5
|
| /bionic/libc/arch-arm/generic/bionic/ |
| memcmp.S | 87 orrs r3, ip
98 orrs r3, ip
|
| /external/valgrind/none/tests/arm/ |
| v6intThumb.stdout.exp | 140 ORRS-16 0x10C
141 orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 0, cpsr 0x00000000
142 orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 0, cpsr 0x40000000 Z
143 orrs r1, r2 :: rd 0x00000001 rm 0x00000000, c:v-in 0, cpsr 0x00000000
144 orrs r1, r2 :: rd 0x00000001 rm 0x00000001, c:v-in 0, cpsr 0x00000000
145 orrs r1, r2 :: rd 0x80000000 rm 0x00000000, c:v-in 0, cpsr 0x80000000 N
146 orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
147 orrs r1, r2 :: rd 0x80000000 rm 0x80000000, c:v-in 0, cpsr 0x80000000 N
148 orrs r1, r2 :: rd 0x37595f2f rm 0x27181728, c:v-in 1, cpsr 0x10000000 V
149 orrs r1, r2 :: rd 0x00000000 rm 0x00000000, c:v-in 1, cpsr 0x50000000 Z
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_mb_neon.asm | 389 orrs r5, r5, r6 ; Check for 0
442 orrs r5, r5, r6 ; Check for 0
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_mb_lpf_neon.asm | 389 orrs r5, r5, r6 ; Check for 0
442 orrs r5, r5, r6 ; Check for 0
|
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm.S | [all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32_test.cc | 743 TEST_F(AssemblerArm32Test, Orrs) {
744 T4Helper(&arm::Arm32Assembler::orrs, true, "orr{cond}s {reg1}, {reg2}, {shift}", "orrs");
|
| assembler_arm.h | 513 virtual void orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { function in class:art::arm::ArmAssembler
[all...] |
| /art/compiler/utils/ |
| assembler_thumb_test.cc | 262 __ orrs(R0, R0, ShifterOperand(R1));
294 __ orrs(R0, R0, ShifterOperand(R8));
316 __ orrs(R0, R0, ShifterOperand(R1), arm::EQ);
[all...] |
