| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32-dsp.s | 33 precequ.ph.qbr $23,$24
37 preceu.ph.qbr $27,$28
65 muleu_s.ph.qbr $15,$16,$17
70 dpau.h.qbr $ac1,$20,$21
72 dpsu.h.qbr $ac3,$22,$23
|
| micromips@mips32-dsp.d | 34 0+005c <[^>]*> 02f8 913c precequ\.ph\.qbr s7,t8
38 0+006c <[^>]*> 037c d13c preceu\.ph\.qbr k1,gp
66 0+00dc <[^>]*> 0230 78d5 muleu_s\.ph\.qbr t7,s0,s1
71 0+00f0 <[^>]*> 02b4 70bc dpau\.h\.qbr \$ac1,s4,s5
73 0+00f8 <[^>]*> 02f6 f4bc dpsu\.h\.qbr \$ac3,s6,s7
|
| mips32-dsp.d | 33 0+005c <[^>]*> 7c18b952 precequ\.ph\.qbr s7,t8
37 0+006c <[^>]*> 7c1cdf52 preceu\.ph\.qbr k1,gp
65 0+00dc <[^>]*> 7e1179d0 muleu_s\.ph\.qbr t7,s0,s1
70 0+00f0 <[^>]*> 7e9509f0 dpau\.h\.qbr \$ac1,s4,s5
72 0+00f8 <[^>]*> 7ed71bf0 dpsu\.h\.qbr \$ac3,s6,s7
|
| mipsr6@mips32-dsp.d | 34 0+005c <[^>]*> 7c18b952 precequ\.ph\.qbr s7,t8
38 0+006c <[^>]*> 7c1cdf52 preceu\.ph\.qbr k1,gp
66 0+00dc <[^>]*> 7e1179d0 muleu_s\.ph\.qbr t7,s0,s1
71 0+00f0 <[^>]*> 7e9509f0 dpau\.h\.qbr \$ac1,s4,s5
73 0+00f8 <[^>]*> 7ed71bf0 dpsu\.h\.qbr \$ac3,s6,s7
|
| /external/llvm/test/MC/Mips/micromips-dsp/ |
| valid.s | 16 dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
43 precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
47 preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
79 dpsu.h.qbr $ac1, $4, $6 # CHECK: dpsu.h.qbr $ac1, $4, $6 # encoding: [0x00,0xc4,0x74,0xbc]
83 muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5
[all...] |
| /external/llvm/test/MC/Mips/dsp/ |
| valid.s | 28 dpau.h.qbr $ac1, $11, $12 # CHECK: dpau.h.qbr $ac1, $11, $12 # encoding: [0x7d,0x6c,0x09,0xf0]
32 dpsu.h.qbr $ac1, $7, $8 # CHECK: dpsu.h.qbr $ac1, $7, $8 # encoding: [0x7c,0xe8,0x0b,0xf0]
74 muleu_s.ph.qbr $fp, $ra, $1 # CHECK: muleu_s.ph.qbr $fp, $ra, $1 # encoding: [0x7f,0xe1,0xf1,0xd0]
88 precequ.ph.qbr $23, $24 # CHECK: precequ.ph.qbr $23, $24 # encoding: [0x7c,0x18,0xb9,0x52]
92 preceu.ph.qbr $27, $gp # CHECK: preceu.ph.qbr $27, $gp # encoding: [0x7c,0x1c,0xdf,0x52
[all...] |
| /external/llvm/test/MC/Mips/micromips-dspr2/ |
| valid.s | 28 dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
56 precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
60 preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
109 dpsu.h.qbr $ac1, $4, $6 # CHECK: dpsu.h.qbr $ac1, $4, $6 # encoding: [0x00,0xc4,0x74,0xbc]
122 muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5
[all...] |
| /external/llvm/test/MC/Mips/dspr2/ |
| valid.s | 45 dpau.h.qbr $ac1, $11, $12 # CHECK: dpau.h.qbr $ac1, $11, $12 # encoding: [0x7d,0x6c,0x09,0xf0]
53 dpsu.h.qbr $ac1, $7, $8 # CHECK: dpsu.h.qbr $ac1, $7, $8 # encoding: [0x7c,0xe8,0x0b,0xf0]
98 muleu_s.ph.qbr $fp, $ra, $1 # CHECK: muleu_s.ph.qbr $fp, $ra, $1 # encoding: [0x7f,0xe1,0xf1,0xd0]
116 precequ.ph.qbr $23,$24 # CHECK: precequ.ph.qbr $23, $24 # encoding: [0x7c,0x18,0xb9,0x52]
120 preceu.ph.qbr $27,$28 # CHECK: preceu.ph.qbr $27, $gp # encoding: [0x7c,0x1c,0xdf,0x52
[all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| invalid-dsp.s | 29 dpau.h.qbr $ac1,$s7,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 dpsu.h.qbr $ac2,$a1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 muleu_s.ph.qbr $a1,$ra,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
69 precequ.ph.qbr $ra,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
73 preceu.ph.qbr $gp,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-dspr2.s | 42 dpau.h.qbr $ac1,$s7,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
50 dpsu.h.qbr $ac2,$a1,$s6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
80 muleu_s.ph.qbr $a1,$ra,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
94 precequ.ph.qbr $ra,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
98 preceu.ph.qbr $gp,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2.S | 926 preceu.ph.qbr t0, t0 // t0 = 0|A3|0|A2
927 preceu.ph.qbr t2, t2 // t2 = 0|B3|0|B2
[all...] |
| /external/aac/libAACenc/src/ |
| adj_thr.cpp | 2130 INT qmin, qbr, qbres, qmbr; local
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| mips-opc.c | [all...] |
