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Searched
refs:setReg
(Results
1 - 25
of
74
) sorted by null
1
2
3
/external/llvm/lib/CodeGen/
AntiDepBreaker.h
61
MI->getOperand(0).
setReg
(NewReg);
MachineRegisterInfo.cpp
297
O.
setReg
(ToReg);
438
nextI = std::next(I); // I is invalidated by the
setReg
441
UseMI->getOperand(0).
setReg
(0U);
TailDuplication.cpp
442
MO.
setReg
(NewReg);
449
MO.
setReg
(VI->second);
518
II->getOperand(Idx).
setReg
(SrcReg);
530
II->getOperand(Idx).
setReg
(Reg);
[
all
...]
PeepholeOptimizer.cpp
549
UseMO->
setReg
(NewVR);
808
MOSrc.
setReg
(NewReg);
[
all
...]
/external/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp
236
MI->getOperand(0).
setReg
(KilledProdReg);
237
MI->getOperand(1).
setReg
(KilledProdReg);
238
MI->getOperand(3).
setReg
(AddendSrcReg);
239
MI->getOperand(2).
setReg
(OtherProdReg);
PPCMIPeephole.cpp
154
MI.getOperand(1).
setReg
(DefMI->getOperand(1).getReg());
155
MI.getOperand(2).
setReg
(DefMI->getOperand(2).getReg());
PPCVSXCopy.cpp
126
SrcMO.
setReg
(NewVReg);
148
SrcMO.
setReg
(NewVReg);
/external/llvm/lib/Target/WebAssembly/
WebAssemblyPeephole.cpp
77
MO.
setReg
(NewReg);
WebAssemblyStoreResults.cpp
115
O.
setReg
(ToReg);
/external/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.cpp
327
Rt.
setReg
(getHexagonRegisterPair(Rt.getReg(), RI));
338
Rt.
setReg
(getHexagonRegisterPair(Rt.getReg(), RI));
350
Rt.
setReg
(getHexagonRegisterPair(Rt.getReg(), RI));
362
Rs.
setReg
(getHexagonRegisterPair(Rs.getReg(), RI));
487
MO.
setReg
(High);
499
MO.
setReg
(High);
512
MO.
setReg
(High);
544
Rt.
setReg
(getHexagonRegisterPair(Rt.getReg(), RI));
HexagonPeephole.cpp
257
MI->getOperand(0).
setReg
(PeepholeSrc);
287
MI->getOperand(PR).
setReg
(POrig);
310
Dst.
setReg
(Src.getReg());
/external/llvm/lib/Target/AArch64/
AArch64DeadRegisterDefinitionsPass.cpp
123
MO.
setReg
(NewReg);
AArch64A57FPLoadBalancing.cpp
569
U.
setReg
(Substs[OrigReg]);
595
MO.
setReg
(Reg);
/external/llvm/lib/Target/Sparc/
DelaySlotFiller.cpp
382
AddMI->getOperand(0).
setReg
(reg - SP::I0 + SP::O0);
421
OrMI->getOperand(0).
setReg
(reg - SP::I0 + SP::O0);
455
RestoreMI->getOperand(0).
setReg
(reg - SP::I0 + SP::O0);
456
RestoreMI->getOperand(1).
setReg
(SP::G0);
SparcRegisterInfo.cpp
194
MI.getOperand(2).
setReg
(SrcOddReg);
207
MI.getOperand(0).
setReg
(DestOddReg);
/external/llvm/lib/Target/AMDGPU/
R600EmitClauseMarkers.cpp
165
Consts[i].first->
setReg
(
169
Consts[i].first->
setReg
(
SIFixSGPRCopies.cpp
214
MI.getOperand(0).
setReg
(CopyUse.getOperand(0).getReg());
232
MI.getOperand(I).
setReg
(TmpReg);
R600ExpandSpecialInstrs.cpp
88
DstOp.
setReg
(AMDGPU::OQAP);
94
Mov->getOperand(MovPredSelIdx).
setReg
(
R600InstrInfo.cpp
978
MO2.
setReg
(AMDGPU::PRED_SEL_ONE);
981
MO2.
setReg
(AMDGPU::PRED_SEL_ZERO);
1015
.
setReg
(Pred[2].getReg());
1017
.
setReg
(Pred[2].getReg());
1019
.
setReg
(Pred[2].getReg());
1021
.
setReg
(Pred[2].getReg());
[
all
...]
/external/llvm/lib/Target/Mips/
MipsOptimizePICCall.cpp
138
I->getOperand(0).
setReg
(DstReg);
229
getCallTargetRegOpnd(*I)->
setReg
(getReg(Entry));
/external/llvm/lib/Target/SystemZ/
SystemZShortenInst.cpp
90
MI.getOperand(0).
setReg
(SystemZMC::getRegAsGR64(Reg));
95
MI.getOperand(0).
setReg
(SystemZMC::getRegAsGR64(Reg));
/external/mesa3d/src/gallium/drivers/radeon/
R600InstrInfo.cpp
427
MO2.
setReg
(AMDGPU::PRED_SEL_ONE);
430
MO2.
setReg
(AMDGPU::PRED_SEL_ZERO);
462
PMO.
setReg
(Pred[2].getReg());
/external/llvm/include/llvm/MC/
MCInst.h
69
void
setReg
(unsigned Reg) {
/external/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp
[
all
...]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCodeEmitter.cpp
119
HMB.getOperand(i).
setReg
(RegMap[Reg - 16]);
158
MCO.
setReg
(Offset + Hexagon::R0);
Completed in 625 milliseconds
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