| /art/compiler/utils/arm/ |
| assembler_arm.cc | 96 uint32_t shift_type;
99 shift_type = static_cast<uint32_t>(shift_);
103 shift_type = static_cast<uint32_t>(arm::Shift::ROR); // Same encoding as ROR.
107 shift_type = static_cast<uint32_t>(shift_);
113 shift_type << kShiftShift |
118 shift_type << kShiftShift | (1 << 4) |
[all...] |
| /external/gemmlowp/meta/generators/ |
| neon_emitter.py | 323 def EmitVShl(self, shift_type, destination, source, shift):
324 self.EmitOp3('vshl.%s' % shift_type, destination, source, shift)
|
| /art/disassembler/ |
| disassembler_arm.cc | 695 uint32_t shift_type = ((instr >> 4) & 0x3); local
785 bool noShift = (imm5 == 0 && shift_type != 0x3);
788 switch (shift_type) {
800 if (shift_type != 0x3 /* rrx */) {
801 args << StringPrintf(" #%d", (0 != imm5 || 0 == shift_type) ? imm5 : 32);
[all...] |
| /external/v8/src/arm64/ |
| simulator-arm64.cc | 913 T Simulator::ShiftOperand(T value, Shift shift_type, unsigned amount) {
920 switch (shift_type) {
1417 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); local
1464 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); local
[all...] |
| simulator-arm64.h | 697 Shift shift_type,
|
| /external/valgrind/VEX/priv/ |
| guest_arm_toIR.c | 9066 UInt regD = 99, regN = 99, regM = 99, imm5 = 99, shift_type = 99; local
9126 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local
9184 UInt regD = 99, regN = 99, shift_type = 99, imm5 = 99, sat_imm = 99; local
[all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.h | [all...] |
| simulator-a64.cc | 317 Shift shift_type,
323 switch (shift_type) {
966 Shift shift_type = static_cast<Shift>(instr->ShiftDP()); local
968 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
[all...] |
| /external/v8/src/arm/ |
| simulator-arm.cc | 2672 int32_t shift_type = instr->Bit(6); local
[all...] |
