/toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/ |
vle-reloc-def-1.s | 10 .globl sub5 11 sub5: label
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vle-reloc-1.s | 17 e_bc 0,5,sub5 18 e_bcl 1,10,sub5
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vle-reloc-def-2.s | 11 .globl sub5 12 sub5: label
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vle-reloc-1.d | 19 1800068: 7a 05 00 0c e_ble cr1,1800074 <sub5> 20 180006c: 7a 1a 00 09 e_beql cr2,1800074 <sub5> 28 01800074 <sub5>:
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vle-reloc-2.d | 86 018001bc <sub5>:
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/external/clang/test/Sema/ |
typecheck-binop.c | 21 int sub5(void *P, int *Q) { function
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/external/llvm/lib/Target/AMDGPU/ |
AMDGPURegisterInfo.cpp | 48 AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
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SIInstrInfo.cpp | 324 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 338 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
vle-reloc.s | 9 e_bc 0,5,sub5 10 e_bcl 1,10,sub5
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vle-reloc.d | 23 10: R_PPC_VLE_REL15 sub5 25 14: R_PPC_VLE_REL15 sub5
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/external/mesa3d/src/gallium/drivers/radeon/ |
SIGenRegisterInfo.pl | 38 def sub5 : SubRegIndex; 59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
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/external/opencv3/modules/viz/test/ |
tests_simple.cpp | 269 std::vector<Affine3d> path = generate_test_trajectory<double>(), sub0, sub1, sub2, sub3, sub4, sub5; local 277 Mat(path).rowRange(33*size/40, 9*size/10).copyTo(sub5); 287 viz.showWidget("sub5", WTrajectoryFrustums(sub5, Vec2d(0.78, 0.78), 0.15));
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/toolchain/binutils/binutils-2.25/include/opcode/ |
nds32.h | 62 #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ 65 | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))
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