| /toolchain/binutils/binutils-2.25/gas/config/ |
| xtensa-relax.h | 44 TransitionList **table; /* Possible transitions for each opcode. */
158 xtensa_opcode opcode; /* Unused for LITERAL_DEF or LABEL_DEF. */ member in struct:build_instr
165 xtensa_opcode opcode; member in struct:transition_rule
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| i370.h | 1 /* i370.h -- Header file for S/390 opcode table
26 /* The opcode table is an array of struct i370_opcode. */
36 /* The opcode name. */
42 /* The opcode itself. Those bits which will be filled in with
44 i370_insn_t opcode; member in struct:i370_opcode
46 /* The opcode mask. This is used by the disassembler. This is a
48 opcode field, and zeroes indicating those bits which need not
52 /* One bit flags for the opcode. These are used to indicate which
63 /* The table itself is sorted by major opcode number, and is otherwise
71 /* Opcode is defined for the original 360 architecture. *
[all...] |
| i960.h | 55 /* Generate the 12-bit opcode for a REG format instruction by placing the
62 /* Generate a template for a REG format instruction: place the opcode bits
136 long opcode; /* 32 bits, constant fields filled in, rest zeroed */ member in struct:i960_opcode
404 * the indicated opcode, and the second a 'bno'.
525 /* end of i960-opcode.h */
|
| mn10300.h | 1 /* mn10300.h -- Header file for Matsushita 10300 opcode table
25 /* The opcode table is an array of struct mn10300_opcode. */
30 /* The opcode name. */
33 /* The opcode itself. Those bits which will be filled in with
35 unsigned long opcode; member in struct:mn10300_opcode
37 /* The opcode mask. This is used by the disassembler. This is a
39 opcode field, and zeroes indicating those bits which need not
50 /* The format of this opcode. */
53 /* Bitmask indicating what cpu variants this opcode is available on.
64 /* The table itself is sorted by major opcode number, and is otherwis
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| avr-dis.c | 33 char *opcode; member in struct:avr_opcodes_s
39 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
40 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
44 #include "opcode/avr.h"
288 const struct avr_opcodes_s *opcode; local
315 for (opcode = avr_opcodes, maskptr = avr_bin_masks;
316 opcode->name;
317 opcode++, maskptr++)
323 for (s = opcode->opcode; *s; ++s
[all...] |
| h8300-dis.c | 25 #include "opcode/h8300.h"
33 const struct h8_opcode *opcode; member in struct:h8_instruction
67 pi->opcode = p;
72 pi->opcode = p;
319 /* Find the first entry in the table for this opcode. */
349 /* Find the exact opcode/arg combo. */
350 for (qi = h8_instructions; qi->opcode->name; qi++)
352 const struct h8_opcode *q = qi->opcode;
665 if (strcmp (qi->opcode->name, "adds") == 0
666 || strcmp (qi->opcode->name, "subs") == 0
[all...] |
| i960-dis.c | 73 /* Divide instruction set into classes based on high 4 bits of opcode. */
115 int opcode;
128 /* Divide instruction set into classes based on high 4 bits of opcode. */
371 for (i = 0; mem_init[i].opcode != 0; i++)
373 j = mem_init[i].opcode - MEM_MIN;
466 int opcode;
484 If an opcode mnemonic begins with "F", it is a floating-point
485 opcode (the "F" is not printed). */
692 for (i = 0; reg_init[i].opcode != 0; i++)
694 j = reg_init[i].opcode - REG_MIN
114 int opcode; member in struct:sparse_tabent
465 int opcode; local
[all...] |
| m68hc11-dis.c | 26 #include "opcode/m68hc11.h"
242 const struct m68hc11_opcode *opcode; local
255 /* Scan the opcode table until we find the opcode
257 opcode = m68hc11_opcodes;
258 for (i = 0; i < m68hc11_num_opcodes; i++, opcode++)
260 if ((opcode->opcode != (code & opcode->xg_mask)) || (opcode->arch != cpuxgate)
[all...] |
| nds32-dis.c | 33 #include "opcode/nds32.h"
224 /* Dump instruction. If the opcode is unknown, return FALSE. */
254 func (stream, "%s", opc->opcode);
260 func (stream, "%s ", opc->opcode);
268 func (stream, "%s.", opc->opcode);
270 func (stream, "%s", opc->opcode);
272 func (stream, "%s ", opc->opcode);
588 /* Get the final correct opcode and parse. */
590 uint32_t opcode = nds32_mask_opcode (insn); local
591 opc = (struct nds32_opcode *) htab_find (opcode_htab, &opcode);
603 uint32_t opcode; local
694 uint32_t opcode = N32_OP6 (insn); local
[all...] |
| nios2-dis.c | 25 #include "opcode/nios2.h"
41 /* Data structures used by the opcode hash table. */
44 const struct nios2_opcode *opcode; member in struct:_nios2_opcode_hash
51 /* Extract the opcode from an instruction word. */
82 /* Function to initialize the opcode hash table. */
119 new_hash->opcode = op;
135 printf ("%s ", tmp_hash->opcode->name);
147 printf ("%s ", tmp_hash->opcode->name);
156 word OPCODE for bfd machine MACH, or NULL if there is an error. */
158 nios2_find_opcode_hash (unsigned long opcode,
[all...] |
| ppc-dis.c | 28 #include "opcode/ppc.h"
335 /* Calculate opcode table indices to speed up disassembly,
347 unsigned op = PPC_OP (powerpc_opcodes[i].opcode);
363 unsigned op = VLE_OP (vle_opcodes[i].opcode, vle_opcodes[i].mask);
458 /* Find a match for INSN in the opcode table, given machine DIALECT.
459 A DIALECT of -1 is special, matching all machine opcode variations. */
464 const struct powerpc_opcode *opcode; local
468 /* Get the major opcode of the instruction. */
471 /* Find the first match in the opcode table for this major opcode. *
509 const struct powerpc_opcode *opcode; local
569 const struct powerpc_opcode *opcode; local
[all...] |
| s390-mkopc.c | 1 /* s390-mkopc.c -- Generates opcode table out of s390-opc.txt
48 char opcode[16]; member in struct:op_struct
70 /* `insertOpcode': insert an op_struct into sorted opcode array. */
73 insertOpcode (char *opcode, char *mnemonic, char *format,
88 str = opcode;
111 strcpy(op_array[ix].opcode, opcode);
171 /* As with insertOpcode instructions are added to the sorted opcode
178 insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,
192 insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits)
336 char opcode[16]; local
[all...] |
| tic4x-dis.c | 28 #include "opcode/tic4x.h"
169 unsigned long opcode)
171 return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
420 p->opcode);
516 p->opcode);
612 && optable_special[i]->opcode == inst->opcode)
622 /* Add the new opcode. */
642 int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE) local
[all...] |
| tic54x-dis.c | 27 #include "opcode/tic54x.h"
52 unsigned short opcode; local
63 opcode = bfd_getl16 (opbuf);
64 tm = tic54x_get_insn (info, memaddr, opcode, &size);
73 if (!print_parallel_instruction (info, memaddr, opcode, tm, size))
78 if (!print_instruction (info, memaddr, opcode,
110 if (tm->opcode == (memdata & tm->mask))
115 /* if lk addressing is used, the second half of the opcode gets
140 if (tm->opcode == (memdata & tm->mask))
172 unsigned short opcode,
[all...] |
| vax-dis.c | 25 #include "opcode/vax.h"
330 invalid operand was found, or -2 if an opcode tabel error was
404 the last opcode might be a single byte with no argument data. */
447 vax_opcodeT opcode = votp->detail.code; local
450 if ((bfd_byte) opcode == buffer[0]
451 && (opcode >> 8 == 0 || opcode >> 8 == buffer[1]))
|
| /external/jacoco/ |
| asm-debug-all-5.0.1.jar | |
| /prebuilts/tools/common/m2/repository/org/ow2/asm/asm-debug-all/5.0.1/ |
| asm-debug-all-5.0.1.jar | |
| /prebuilts/tools/common/m2/repository/org/ow2/asm/asm-debug-all/5.0.2/ |
| asm-debug-all-5.0.2.jar | |
| /prebuilts/tools/common/m2/repository/org/ow2/asm/asm-debug-all/5.0.4/ |
| asm-debug-all-5.0.4.jar | |
| /prebuilts/tools/common/offline-m2/org/ow2/asm/asm-debug-all/5.0.1/ |
| asm-debug-all-5.0.1.jar | |
| /art/runtime/quick/ |
| inline_method_analyser.cc | 60 template <Instruction::Code opcode> bool Opcode();
112 template <Instruction::Code opcode>
113 bool Matcher::Opcode() {
114 return instruction_->Opcode() == opcode;
119 return IsInstructionDirectConst(instruction_->Opcode()) &&
120 (instruction_->Opcode() == Instruction::CONST_WIDE ? instruction_->VRegB_51l() == 0
126 return IsInstructionIPut(instruction_->Opcode()) &&
144 DCHECK_EQ(invoke_direct->Opcode(), Instruction::INVOKE_DIRECT)
468 Instruction::Code opcode = instruction->Opcode(); local
599 Instruction::Code opcode = instruction->Opcode(); local
664 Instruction::Code opcode = instruction->Opcode(); local
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/program/ |
| CodeTranslator.java | 24 import dexfuzz.rawdex.Opcode;
554 nop.insn.info = Instruction.getOpcodeInfo(Opcode.NOP);
567 * Determine if a particular instruction is a branch instruction, based on opcode.
570 Opcode opcode = insn.info.opcode; local
571 if (Opcode.isBetween(opcode, Opcode.IF_EQ, Opcode.IF_LEZ
582 Opcode opcode = insn.info.opcode; local
[all...] |
| /bionic/libc/kernel/uapi/linux/ |
| ndctl.h | 59 __u32 opcode; member in struct:nd_cmd_vendor_hdr
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| InsnFormat.java | 39 * flag to enable/disable the new extended opcode formats; meant as a
476 * Helper method to combine an opcode and a second byte of data into
479 * @param insn {@code non-null;} the instruction containing the opcode
488 int opcode = insn.getOpcode().getOpcode(); local
490 if ((opcode & 0xff) != opcode) {
491 throw new IllegalArgumentException("opcode out of range 0..255");
494 return (short) (opcode | (arg << 8));
498 * Helper method to get an extended (16-bit) opcode out of an
499 * instruction, returning it as a code unit. The opcode
507 int opcode = insn.getOpcode().getOpcode(); local
[all...] |
| /dalvik/dx/src/com/android/dx/dex/file/ |
| DebugInfoDecoder.java | 294 int opcode = bs.readByte() & 0xff; local
296 switch (opcode) {
399 if (opcode < DBG_FIRST_SPECIAL) {
401 "Invalid extended opcode encountered "
402 + opcode);
405 int adjopcode = opcode - DBG_FIRST_SPECIAL;
|
