| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | 85 switch (AddressingModeField::decode(instr_->opcode())) {
113 switch (AddressingModeField::decode(instr_->opcode())) {
142 switch (AddressingModeField::decode(instr_->opcode())) {
490 InstructionCode opcode = instr->opcode(); local
491 switch (ArchOpcodeField::decode(opcode)) {
569 int const num_parameters = MiscField::decode(instr->opcode());
599 Deoptimizer::BailoutType(MiscField::decode(instr->opcode()));
617 static_cast<RecordWriteMode>(MiscField::decode(instr->opcode()));
660 if (FlagsModeField::decode(opcode) != kFlags_none)
1240 ArchOpcode opcode = instr->arch_opcode(); local
[all...] |
| /external/v8/src/compiler/ia32/ |
| instruction-selector-ia32.cc | 31 switch (node->opcode()) {
57 if (base->opcode() == IrOpcode::kInt32Constant) {
130 void VisitRO(InstructionSelector* selector, Node* node, ArchOpcode opcode) {
132 selector->Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
137 InstructionCode opcode) {
139 selector->Emit(opcode, g.DefineAsRegister(node),
174 ArchOpcode opcode = kArchNop; local
177 opcode = kIA32Movss;
180 opcode = kIA32Movsd;
184 opcode = load_rep.IsSigned() ? kIA32Movsxbl : kIA32Movzxbl
259 ArchOpcode opcode = kArchNop; local
313 ArchOpcode opcode = kArchNop; local
359 ArchOpcode opcode = kArchNop; local
547 InstructionCode opcode = AddressingModeField::encode(mode) | kIA32Lea; local
618 InstructionCode opcode = AddressingModeField::encode(mode) | kIA32Lea; local
1038 InstructionCode opcode = cont->Encode(kIA32StackCheck); local
[all...] |
| /external/v8/src/compiler/ |
| instruction-selector.cc | 51 if (phi->opcode() != IrOpcode::kPhi) continue;
119 Instruction* InstructionSelector::Emit(InstructionCode opcode,
124 return Emit(opcode, output_count, &output, 0, nullptr, temp_count, temps);
128 Instruction* InstructionSelector::Emit(InstructionCode opcode,
133 return Emit(opcode, output_count, &output, 1, &a, temp_count, temps);
137 Instruction* InstructionSelector::Emit(InstructionCode opcode,
145 return Emit(opcode, output_count, &output, input_count, inputs, temp_count,
150 Instruction* InstructionSelector::Emit(InstructionCode opcode,
159 return Emit(opcode, output_count, &output, input_count, inputs, temp_count,
165 InstructionCode opcode, InstructionOperand output, InstructionOperand a
1416 InstructionCode opcode = kArchNop; local
1465 InstructionCode opcode; local
1506 InstructionCode opcode; local
1573 InstructionCode opcode = kArchDeoptimize; local
[all...] |
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | 104 switch (AddressingModeField::decode(instr_->opcode())) {
490 InstructionCode opcode = instr->opcode(); local
492 switch (ArchOpcodeField::decode(opcode)) {
555 int const num_parameters = MiscField::decode(instr->opcode());
565 int const num_parameters = MiscField::decode(instr->opcode());
594 Deoptimizer::BailoutType(MiscField::decode(instr->opcode()));
612 static_cast<RecordWriteMode>(MiscField::decode(instr->opcode()));
632 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
638 // Pseudo-instruction used for overflow/branch. No opcode emitted here
[all...] |
| instruction-selector-mips.cc | 27 InstructionOperand UseOperand(Node* node, InstructionCode opcode) {
28 if (CanBeImmediate(node, opcode)) {
34 bool CanBeImmediate(Node* node, InstructionCode opcode) {
38 switch (ArchOpcodeField::decode(opcode)) {
64 static void VisitRRR(InstructionSelector* selector, ArchOpcode opcode,
67 selector->Emit(opcode, g.DefineAsRegister(node),
73 static void VisitRR(InstructionSelector* selector, ArchOpcode opcode,
76 selector->Emit(opcode, g.DefineAsRegister(node),
81 static void VisitRRO(InstructionSelector* selector, ArchOpcode opcode,
84 selector->Emit(opcode, g.DefineAsRegister(node)
135 ArchOpcode opcode = kArchNop; local
215 ArchOpcode opcode = kArchNop; local
855 ArchOpcode opcode = kArchNop; local
902 ArchOpcode opcode = kArchNop; local
1141 InstructionCode const opcode = cont->Encode(kMipsCmp); local
[all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | 104 switch (AddressingModeField::decode(instr_->opcode())) {
502 InstructionCode opcode = instr->opcode(); local
504 switch (ArchOpcodeField::decode(opcode)) {
565 int const num_parameters = MiscField::decode(instr->opcode());
575 int const num_parameters = MiscField::decode(instr->opcode());
604 Deoptimizer::BailoutType(MiscField::decode(instr->opcode()));
622 static_cast<RecordWriteMode>(MiscField::decode(instr->opcode()));
645 // Pseudo-instruction used for overflow/branch. No opcode emitted here.
654 // Pseudo-instruction used for overflow/branch. No opcode emitted here
[all...] |
| /external/v8/src/compiler/ppc/ |
| code-generator-ppc.cc | 84 *mode = AddressingModeField::decode(instr_->opcode());
669 ArchOpcode opcode = ArchOpcodeField::decode(instr->opcode()); local
671 switch (opcode) {
751 int const num_parameters = MiscField::decode(instr->opcode());
761 int const num_parameters = MiscField::decode(instr->opcode());
794 Deoptimizer::BailoutType(MiscField::decode(instr->opcode()));
[all...] |
| /external/v8/src/compiler/x87/ |
| instruction-selector-x87.cc | 35 switch (node->opcode()) {
61 if (base->opcode() == IrOpcode::kInt32Constant) {
135 ArchOpcode opcode = kArchNop; local
138 opcode = kX87Movss;
141 opcode = kX87Movsd;
145 opcode = load_rep.IsSigned() ? kX87Movsxbl : kX87Movzxbl;
148 opcode = load_rep.IsSigned() ? kX87Movsxwl : kX87Movzxwl;
152 opcode = kX87Movl;
167 InstructionCode code = opcode | AddressingModeField::encode(mode);
220 ArchOpcode opcode = kArchNop local
274 ArchOpcode opcode = kArchNop; local
320 ArchOpcode opcode = kArchNop; local
508 InstructionCode opcode = AddressingModeField::encode(mode) | kX87Lea; local
576 InstructionCode opcode = AddressingModeField::encode(mode) | kX87Lea; local
1055 InstructionCode opcode = cont->Encode(kX87StackCheck); local
[all...] |
| /external/v8/src/ia32/ |
| disasm-ia32.cc | 745 byte opcode = *data; local
750 switch (opcode) {
822 switch (opcode) {
859 switch (opcode) {
897 switch (opcode) {
937 switch (opcode) {
959 switch (opcode) {
976 switch (opcode) {
989 switch (opcode) {
1006 switch (opcode) {
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.h | 488 uint32_t opcode = ((instr & kOpcodeMask)); local
495 bool sllzz = (opcode == SLL &&
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.h | 516 uint32_t opcode = ((instr & kOpcodeMask)); local
523 bool sllzz = (opcode == SLL &&
[all...] |
| /external/v8/src/wasm/ |
| ast-decoder.cc | 40 WasmOpcode opcode() const { return static_cast<WasmOpcode>(*pc); } function in struct:v8::internal::wasm::Tree
49 WasmOpcode opcode() const { return static_cast<WasmOpcode>(*pc()); } function in struct:v8::internal::wasm::Production
307 WasmOpcode opcode = static_cast<WasmOpcode>(*pc_); local
309 indentation(), startrel(pc_), opcode,
310 WasmOpcodes::OpcodeName(opcode));
312 FunctionSig* sig = WasmOpcodes::Signature(opcode);
327 switch (opcode) {
573 error("Invalid opcode");
632 WasmOpcodes::OpcodeName(tree->opcode()),
648 WasmOpcode opcode = p->opcode() local
[all...] |
| /external/v8/test/cctest/compiler/ |
| test-simplified-lowering.cc | 702 CHECK_EQ(expected, node->opcode());
709 CHECK_EQ(expected, node->opcode());
717 CHECK_EQ(expected, node->opcode());
819 CHECK_EQ(t.machine()->Word32Equal()->opcode(), cmp->opcode());
834 CHECK_EQ(IrOpcode::kChangeBitToBool, use->InputAt(0)->opcode());
836 CHECK_EQ(t.machine()->Word32Equal()->opcode(), cmp->opcode());
851 CHECK_EQ(t.machine()->WordEqual()->opcode(), cmp->opcode());
1138 IrOpcode::Value opcode = local
[all...] |
| /external/vulkan-validation-layers/layers/ |
| core_validation.cpp | 184 // A forward iterator over spirv instructions. Provides easy access to len, opcode, and content words
191 uint32_t opcode() { return *it & 0x0ffffu; } function in struct:spirv_inst_iter
[all...] |
| /hardware/broadcom/libbt/src/ |
| hardware.c | 622 uint16_t opcode; local
633 STREAM_TO_UINT16(opcode,p);
744 (opcode == HCI_VSC_LAUNCH_RAM))
753 STREAM_TO_UINT16(opcode,p);
754 is_proceeding = bt_vendor_cbacks->xmit_cb(opcode, \
965 uint16_t opcode; local
1567 uint16_t opcode; local
[all...] |
| /system/bt/stack/include/ |
| smp_api.h | 285 UINT16 opcode; member in struct:__anon72804
|
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.cpp | 818 const int opcode = GGL_READ_NEEDS(LOGIC_OP, needs.n) | GGL_CLEAR; local
819 if (opcode == GGL_COPY)
831 switch(opcode) {
967 const int opcode = GGL_READ_NEEDS(LOGIC_OP, needs.n) | GGL_CLEAR; local
[all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| elf32-ip2k.c | 39 unsigned short opcode; member in struct:ip2k_opcode
257 if ((insn & opcodes->mask) == opcodes->opcode)
[all...] |
| elf32-msp430.c | 1874 int opcode; local
[all...] |
| xtensa-isa.c | 244 /* Set up the opcode name lookup table. */
251 isa->opname_lookup_table[n].u.opcode = n;
413 xtensa_opcode opcode;
424 for (opcode = 0; opcode < num_opcodes; opcode++)
426 num_uses = xtensa_opcode_num_funcUnit_uses (isa, opcode);
429 use = xtensa_opcode_funcUnit_use (isa, opcode, i);
649 /* Opcode information. */
657 strcpy (xtisa_error_msg, "invalid opcode specifier");
411 xtensa_opcode opcode; local
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-arc.c | 26 #include "opcode/arc.h"
98 /* Non-zero if opcode tables have been initialized.
184 Opcode selection is deferred until later because we might see a .option
202 /* Initialize the various opcode and operand tables.
342 Remember that the opcode "insertion fns" cannot be used on data, they're
650 int opcode, subopcode;
679 opcode = get_absolute_expression ();
685 as_bad (_("expected comma after opcode"));
702 if (3 != opcode)
704 as_bad (_("subcode value found when opcode not equal 0x03"))
647 int opcode, subopcode; local
1409 const struct arc_opcode *opcode; local
[all...] |
| tc-avr.c | 34 char * opcode; member in struct:avr_opcodes_s
40 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
45 #include "opcode/avr.h"
401 /* Opcode hash table. */
634 struct avr_opcodes_s *opcode; local
639 quick index to the first opcode with a particular name in the opcode
641 for (opcode = avr_opcodes; opcode->name; opcode++
1638 struct avr_opcodes_s *opcode; local
[all...] |
| tc-crx.c | 29 #include "opcode/crx.h"
65 /* Opcode mnemonics hash table. */
403 /* 'opcode' points to the start of the instruction, whether
405 char *opcode = fragP->fr_literal + fragP->fr_fix; local
416 *opcode = 0x7e;
420 *opcode = 0x7f;
427 *++opcode = 0x31;
434 *++opcode = 0x31;
549 has many identical opcode names that have different opcodes based
551 the first opcode with a particular name in the opcode table. *
[all...] |
| tc-d10v.c | 24 #include "opcode/d10v.h"
103 /* Opcode hash table. */
279 struct d10v_opcode *opcode; local
283 has many identical opcode names that have different opcodes based
285 the first opcode with a particular name in the opcode table. */
287 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
289 if (strcmp (prev_name, opcode->name)
1722 struct d10v_opcode *opcode; local
[all...] |
| tc-h8300.c | 29 #include "opcode/h8300.h"
64 const struct h8_opcode *opcode; member in struct:h8_instruction
226 static struct hash_control *opcode_hash_control; /* Opcode mnemonics. */
254 /* We do a minimum amount of sorting on the opcode table; this is to
268 /* Strip off any . part when inserting the opcode and only enter
292 /* A negative TIME is used to indicate that we've added this opcode
320 /* Find the length of the opcode in bytes. */
325 pi->opcode = p;
336 pi->opcode = 0;
1039 /* CONST_xxx are used as placeholders in the opcode table. *
[all...] |
