| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 60 /// Returns true. Spill code for predicate registers might need an extra
|
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 79 // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers.
|
| /external/llvm/lib/Target/Sparc/ |
| SparcSubtarget.cpp | 71 // 16 words for register window spill
|
| /external/llvm/test/CodeGen/ARM/ |
| crash-O0.ll | 7 ; This function would crash RegAllocFast because it tried to spill %CPSR.
|
| /external/llvm/test/CodeGen/MIR/X86/ |
| callee-saved-info.mir | 55 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
|
| expected-named-register-in-callee-saved-register.mir | 52 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' }
|
| expected-stack-object.mir | 44 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16,
|
| frame-info-stack-references.mir | 47 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16,
|
| /external/llvm/test/CodeGen/SPARC/ |
| spill.ll | 7 ;; registers to ensure the spill will happen.
|
| /external/llvm/test/CodeGen/SystemZ/ |
| frame-13.ll | 24 ; emergency spill slots at 160(%r15), the amount that we need to allocate
208 ; Repeat f2 in a case that needs the emergency spill slots (because all
244 ; And again with maximum register pressure. The only spill slots that the
246 ; The FP case needs to spill an extra register and is too dependent on
|
| frame-09.ll | 41 ; This function should require all GPRs but no other spill slots.
111 ; emergency spill slots at 160(%r11), so create a frame of size 524192
|
| /external/llvm/test/CodeGen/X86/ |
| stack-align.ll | 41 ; Use a call to force a spill.
|
| stack-folding-adx-x86_64.ll | 8 ; By including a nop call with sideeffects we can force a partial register spill of the
|
| stack-folding-x86_64.ll | 8 ; By including a nop call with sideeffects we can force a partial register spill of the
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 285 void spill(Instruction *defi, Value *slot, LValue *);
707 SpillCodeInserter& spill; member in class:nv50_ir::GCRA
993 GCRA::GCRA(Function *fn, SpillCodeInserter& spill) :
996 spill(spill)
1153 (node->degree < node->degreeLimit) ? "" : "(spill)");
1171 // spill candidate
1180 ERROR("no viable spill candidates left\n");
1436 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval) function in class:nv50_ir::SpillCodeInserter
[all...] |
| /external/v8/src/compiler/ |
| greedy-allocator.cc | 409 // in the spill ranges.
410 // TODO(mtrofin): should the splinters own their own spill ranges?
482 Spill(range);
523 Spill(second_part);
|
| /frameworks/support/v17/leanback/res/values-nb/ |
| strings.xml | 28 <string name="lb_playback_controls_play" msgid="731953341987346903">"Spill av"</string>
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| emit-rtl.h | 47 /* Set the attributes for MEM appropriate for a spill slot. */
|
| /prebuilts/sdk/current/support/v17/leanback/res/values-nb/ |
| strings.xml | 28 <string name="lb_playback_controls_play" msgid="731953341987346903">"Spill av"</string>
|
| /art/compiler/debug/dwarf/ |
| debug_frame_opcode_writer.h | 72 // Common alias in assemblers - spill relative to current stack pointer.
82 // Custom alias - spill many registers based on bitmask.
|
| /external/libunwind/include/ |
| libunwind-dynamic.h | 64 UNW_DYN_SPILL_FP_REL, /* frame-pointer-relative register spill */
65 UNW_DYN_SPILL_SP_REL, /* stack-pointer-relative register spill */
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
220 /// as currently those new intervals are not guaranteed to spill.
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.cpp | 59 // since these spill to VGPRs.
61 // FIXME: We should be cleaning up these unused SGPR spill frame indices
|
| /external/llvm/test/CodeGen/PowerPC/ |
| aantidep-def-ec.mir | 85 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
86 - { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%x29' }
|
| sjlj.ll | 74 ; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
139 ; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
|
