| /art/runtime/arch/x86/ |
| context_x86.cc | 44 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill.
|
| /art/test/510-checker-try-catch/smali/ |
| Runtime.smali | 387 # These values were forced to spill by an always-throwing try/catch after their
409 # Insert a try/catch to force v1,v2,v3 to spill.
436 # These values were forced to spill by an always-throwing try/catch after their
459 # Insert a try/catch to force (v2, v3), (v4, v5), (v6, v7) to spill.
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| /external/llvm/docs/HistoricalNotes/ |
| 2003-06-26-Reoptimizer2.txt | 39 There is a problem with alloca: we cannot find our spill space for
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| /external/llvm/lib/CodeGen/ |
| PseudoSourceValue.cpp | 70 // Spill slots will not alias any LLVM IR value.
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| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 116 // Determine the sizes of each callee-save spill areas and record which frame
117 // belongs to which callee-save spill areas.
177 // Determine starting offsets of spill areas.
354 // Move SP to start of FP callee save spill area.
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| README-Thumb.txt | 18 temporaries to spill values into.
186 These instructions preserve the condition code which is important if the spill
|
| /external/llvm/lib/Target/SystemZ/ |
| README.txt | 167 We might want to model all access registers and use them to spill
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegColoring.cpp | 62 // Compute the total spill weight for VReg.
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| /external/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.h | 88 /// to spill and restore the frame pointer.
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-spill-lr.ll | 5 ; on the stack this will cause determineCalleeSaves() to spill LR as an
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| /external/llvm/test/CodeGen/ARM/ |
| 2010-05-20-NEONSpillCrash.ll | 3 ; This test would crash the rewriter when trying to handle a spill after one of
|
| struct-byval-frame-index.ll | 3 ; Check a spill right after a function call with large struct byval is correctly
8 ; CHECK: str r{{.*}}, [sp, [[SLOT:#[0-9]+]]] @ 4-byte Spill
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| /external/llvm/test/CodeGen/PowerPC/ |
| addisdtprelha-nonr3.mir | 48 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%x30' }
|
| /external/llvm/test/CodeGen/SystemZ/ |
| frame-01.ll | 23 ; two emergency spill slots at 160(%r15), for instructions with unsigned
|
| frame-14.ll | 24 ; emergency spill slots at 160(%r15), the amount that we need to allocate
229 ; Repeat f4 in a case that needs the emergency spill slots (because all
267 ; And again with maximum register pressure. The only spill slots that the
269 ; The FP case needs to spill an extra register and is too dependent on
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| frame-16.ll | 24 ; emergency spill slots at 160(%r15), the amount that we need to allocate
219 ; Repeat f4 in a case that needs the emergency spill slots (because all
253 ; And again with maximum register pressure. The only spill slots that the
256 ; spill a second register. This leads to an extra displacement of 8.
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| frame-08.ll | 6 ; It is big enough to require two emergency spill slots at 160(%r15),
74 ; It is big enough to require two emergency spill slots at 160(%r15),
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| /external/llvm/test/CodeGen/XCore/ |
| exception.ll | 53 ; N.B. we alloc no variables, hence force compiler to spill
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_wm_debug.c | 92 printf("/SPILL(%x)",inst->dst[i]->spill_slot);
|
| /packages/apps/Settings/res/values-nb/ |
| arrays.xml | 268 <item msgid="1097324338692486211">"spill inn lyd"</item>
269 <item msgid="5031552983987798163">"spill av lyd"</item>
334 <item msgid="1720492593061838172">"Spill inn lyd"</item>
335 <item msgid="3493046322001257041">"Spill av lyd"</item>
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 598 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
602 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
639 // spill + reload via ldc1
649 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
653 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
|
| /art/runtime/entrypoints/quick/ |
| quick_trampoline_entrypoints.cc | 54 // | arg3 spill | | Caller's frame
55 // | arg2 spill | |
56 // | arg1 spill | |
90 // | arg3 spill | | Caller's frame
91 // | arg2 spill | |
92 // | arg1 spill | |
128 // | arg3 spill | | Caller's frame
129 // | arg2 spill | |
130 // | arg1 spill | |
164 // | arg3 spill | | Caller's fram
[all...] |
| /bionic/libc/arch-arm/generic/bionic/ |
| memcpy.S | 100 /* Use post-incriment mode for stm to spill r5-r11 to reserved stack
213 /* Use post-increment mode for stm to spill r5-r11 to reserved stack
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| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 202 REG_S ra, RAOFF(sp) # spill state
311 move s1, a1 # temp spill
|
| /external/llvm/include/llvm/CodeGen/ |
| MIRYamlMapping.h | 207 IO.enumCase(Type, "spill-slot", MachineStackObject::SpillSlot);
257 IO.enumCase(Type, "spill-slot", FixedMachineStackObject::SpillSlot);
|
