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  /external/llvm/test/CodeGen/X86/
pr18846.ll 6 ; pr18846 - needless avx spill/reload
12 ;CHECK-NOT: vmovups {{.*#+}} 32-byte Folded Spill
pr24139.ll 6 ; CHECK: # 16-byte Spill
7 ; CHECK-NOT: # 16-byte Spill
2012-01-10-UndefExceptionEdge.ll 11 ; so the return value can spill.
stackmap.ll 304 ; Spill a subregister stackmap operand.
311 ; Check that the subregister operand is a 4-byte spill.
344 ; we expect the register to be encoded with the proper size and spill offset. We don't know which
  /external/v8/src/compiler/
linkage.cc 355 // unaddressable spill slot. We hack this in the OSR prologue. Fix.
499 // Context. Use the parameter location of the context spill slot.
instruction-selector-impl.h 268 // a spill location on this (callee) frame.
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
opc-m.s 414 st8.spill [r4] = r5
415 st8.spill [r4] = r5, -141
416 st8.spill.nta [r4] = r5
417 st8.spill.nta [r4] = r5, -128
689 stf.spill [r4] = f5
690 stf.spill [r4] = f5, -60
691 stf.spill.nta [r4] = f5
692 stf.spill.nta [r4] = f5, -47
psn.d 271 570: 08 00 74 83 d8 11 \[MMI\] st8.spill \[r65\]=r93
272 576: 00 e8 06 b5 23 00 st8.spill.d1 \[r65\]=r93
274 580: 08 00 74 83 da 11 \[MMI\] st8.spill.d1 \[r65\]=r93
275 586: 00 e8 06 b9 23 00 st8.spill.d2 \[r65\]=r93
277 590: 08 00 74 83 dc 11 \[MMI\] st8.spill.d2 \[r65\]=r93
278 596: 00 e8 06 bd 23 00 st8.spill.nta \[r65\]=r93
280 5a0: 08 00 74 83 de 11 \[MMI\] st8.spill.nta \[r65\]=r93
281 5a6: 00 ec 06 b1 23 00 st8.spill.d4 \[r65\]=r93
283 5b0: 08 00 76 83 da 11 \[MMI\] st8.spill.d5 \[r65\]=r93
284 5b6: 00 ec 06 b9 23 00 st8.spill.d6 \[r65\]=r9
    [all...]
  /external/llvm/include/llvm/CodeGen/PBQP/
ReductionRules.h 153 // An empty or spill only cost vector does not provide any register option.
  /external/llvm/lib/Target/ARM/
ARMMachineFunctionInfo.h 67 /// spill stack offset.
  /external/llvm/lib/Target/Mips/
Mips16FrameLowering.cpp 125 // It's killed at the spill, unless the register is RA and return address
MipsFrameLowering.cpp 131 // callee-saved spill.
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyFrameLowering.cpp 15 /// callee-saved registers to save, and no spill slots.
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmInstrumentation.cpp 54 // to spill both registers before instrumentation code and restore them
58 // PUSH AddressReg # spill AddressReg
59 // PUSH ShadowReg # spill ShadowReg
81 // RCX are checked. In this case there're no need to spill and restore
    [all...]
  /external/llvm/lib/Target/X86/
README-FPStack.txt 64 folding spill code into the instructions.
  /external/llvm/test/CodeGen/SystemZ/
fp-conv-02.ll 75 ; Test a case where we spill the source of at least one LDEBR. We want
fp-conv-03.ll 91 ; Test a case where we spill the source of at least one LXEBR. We want
fp-conv-04.ll 91 ; Test a case where we spill the source of at least one LXDBR. We want
fp-sqrt-01.ll 76 ; Test a case where we spill the source of at least one SQEBR. We want
fp-sqrt-02.ll 78 ; Test a case where we spill the source of at least one SQDBR. We want
  /external/llvm/test/CodeGen/Thumb2/
crash.ll 53 ; Make sure the DPair register class can spill.
  /art/runtime/
stack.h 677 * spill or Method* in bytes using Method*.
696 * | core callee-save spill | {variable sized}
698 * | fp callee-save spill |
  /external/llvm/include/llvm/CodeGen/
RegAllocPBQP.h 32 /// @brief Spill option index.
488 // node exists then the node with the lowest spill-cost:degree ratio is
515 // Conservatively allocatable nodes will never spill. For now just
  /external/llvm/lib/CodeGen/
SjLjEHPrepare.cpp 273 /// edge and spill them.
329 DEBUG(dbgs() << "SJLJ Spill: " << *Inst << " around "
336 // If we decided we need a spill, do it.
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 339 // 2. The RC spill size must not be smaller than our spill size.
340 // 3. RC spill alignment must be compatible with ours.

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