| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs_reg_allocate.cpp | 233 /* Failed to allocate registers. Spill a reg, and the caller will
239 fail("no register to spill\n");
291 * spill. Nothing else will make it up to MRF 14/15.
311 * spill/unspill we'll have to do, and guess that the insides of
322 * registers have a width of 1 so if we try to spill them we'll
383 /* Generate spill/unspill instructions for the objects being
384 * spilled. Right now, we spill or unspill the whole thing to a
386 * could just spill/unspill the GRF being accessed.
|
| /external/v8/test/mjsunit/regress/ |
| regress-crbug-173907.js | 36 function spill() { function
45 spill(); // At this point initial values for phi1 and phi2 are spilled.
|
| /packages/apps/TV/res/values-nb/ |
| arrays.xml | 37 <item msgid="7405041316051047427">"Spill"</item>
51 <item msgid="6484685553679698447">"Spill"</item>
|
| /art/runtime/interpreter/mterp/x86/ |
| entry.S | 37 /* Spill callee save regs */
|
| /art/runtime/interpreter/mterp/x86_64/ |
| entry.S | 37 /* Spill callee save regs */
|
| /art/test/557-checker-ref-equivalent/smali/ |
| TestCase.smali | 38 # broke the invariant of not sharing the same spill slot between those two
|
| /external/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 32 DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
95 // spiller can rematerialize through these copies, so the spill
148 // Don't recompute spill weight for an unspillable register.
208 // Weakly boost the spill weight of hinted registers.
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-2011-03-09-CPSRSpill.ll | 3 ; Can't copy or spill / restore CPSR.
|
| /external/llvm/test/CodeGen/ARM/ |
| gpr-paired-spill-thumbinst.ll | 17 ; Make sure we are actually creating the Thumb versions of the spill
|
| /external/llvm/test/CodeGen/Hexagon/ |
| validate-offset.ll | 5 ; by 'Hexagon Expand Predicate Spill Code' pass.
|
| /external/llvm/test/CodeGen/MIR/Mips/ |
| expected-global-value-or-symbol-after-call-entry.mir | 23 - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4,
|
| /external/llvm/test/CodeGen/MIR/X86/ |
| cfi-offset.mir | 28 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
|
| expected-comma-after-cfi-register.mir | 26 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
|
| expected-register-after-cfi-operand.mir | 26 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
|
| liveout-register-mask.mir | 28 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
|
| /external/llvm/test/CodeGen/PowerPC/ |
| buildvec_canonicalize.ll | 12 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
|
| frame-size.ll | 10 ; Check that the RS spill slot has been allocated (because the estimate
|
| vrspill.ll | 5 ; This verifies that we generate correct spill/reload code for vector regs.
|
| /external/llvm/test/CodeGen/Thumb/ |
| 2011-06-16-NoGPRs.ll | 6 ; to spill them.
|
| /external/llvm/test/CodeGen/Thumb2/ |
| inflate-regs.ll | 7 ; RAGreedy should split the range and use d16-d31 to avoid a spill.
|
| /external/llvm/test/CodeGen/X86/ |
| 2008-01-08-SchedulerCrash.ll | 3 ; Test scheduling a multi-use compare. We should neither spill flags
|
| avx512-bugfix-25270.ll | 13 ; CHECK-NEXT: vmovups %zmm0, (%rsp) ## 64-byte Spill
|
| catchpad-realign-savexmm.ll | 37 ; CHECK: movaps %xmm6, -16(%rbp) # 16-byte Spill
|
| licm-regpressure.ll | 7 ; CHECK-NOT: Spill
|
| patchpoint-verifiable.mir | 28 - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
|
