| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| 476.s | 31 andi. 3,4,0xdead
|
| a2.s | 35 andi. 4,5,6
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| avr.h | 205 AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000)
|
| nios2r1.h | 271 #define MATCH_R1_ANDI MATCH_R1_OP (ANDI)
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| dlx-dis.c | 280 { OPC(ANDIOP), "andi" }, /* Store word. */
|
| nios2-opc.c | 187 {"andi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
|
| sh64-opc.c | 54 /* 110110mmmmmmssssssssssdddddd0000 andi <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
55 { "andi", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd8000000
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 924 andi(rd, rs, rt.imm32_);
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | 1072 andi(rd, rs, static_cast<int32_t>(rt.imm64_));
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 136 // FIXME: Remove these once the ANDI glue bug is fixed:
138 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
[all...] |
| /art/compiler/optimizing/ |
| code_generator_mips.cc | [all...] |
| code_generator_mips64.cc | [all...] |
| /external/valgrind/none/tests/mips32/ |
| MIPS32int.stdout.exp-mips32-BE | 81 ANDI
82 andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
83 andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000
84 andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001
85 andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000
86 andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000
87 andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145
[all...] |
| MIPS32int.stdout.exp-mips32-LE | 81 ANDI
82 andi $t0, $t1, 1 :: rt 0x00000000 rs 0x00000000, imm 0x00000001
83 andi $t0, $t1, 0 :: rt 0x00000000 rs 0x00000001, imm 0x00000000
84 andi $t0, $t1, 1 :: rt 0x00000001 rs 0x00000001, imm 0x00000001
85 andi $t0, $t1, 1 :: rt 0x00000001 rs 0x7fffffff, imm 0x00000000
86 andi $t0, $t1, 0 :: rt 0x00000000 rs 0x80000000, imm 0x00000000
87 andi $t0, $t1, 0x3145 :: rt 0x00003145 rs 0xffffffff, imm 0x00003145
[all...] |
| /external/llvm/test/MC/PowerPC/ |
| ppc64-encoding.s | 557 # CHECK-BE: andi. 2, 3, 128 # encoding: [0x70,0x62,0x00,0x80]
558 # CHECK-LE: andi. 2, 3, 128 # encoding: [0x80,0x00,0x62,0x70]
559 andi. 2, 3, 128
[all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeARM_T2_32.c | 99 #define ANDI 0xf0000000
617 return push_inst32(compiler, ANDI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | nimm);
[all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MicroMips32r6InstrInfo.td | 32 class ANDI_MMR6_ENC : ADDI_FM_MMR6<"andi", 0x34>;
507 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
[all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 142 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
143 0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 148 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
149 0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 145 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
146 0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 145 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
146 0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 184 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
185 0x30 0xc9 0x45 0x67 # CHECK: andi $9, $6, 17767
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 19 andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2]
|
