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  /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/gcov-src/
libgcov-driver.c 766 gcov_unsigned_t bitvector = 0, b_ix = 0; local
773 bitvector |= 1 << b_ix;
776 gcov_write_unsigned (bitvector);
778 bitvector = 0;
782 gcov_write_unsigned (bitvector);
    [all...]
  /prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/lib/gcc/x86_64-linux-android/4.9/gcov-src/
libgcov-driver.c 766 gcov_unsigned_t bitvector = 0, b_ix = 0; local
773 bitvector |= 1 << b_ix;
776 gcov_write_unsigned (bitvector);
778 bitvector = 0;
782 gcov_write_unsigned (bitvector);
    [all...]
  /external/llvm/lib/CodeGen/
MachineLICM.cpp 169 void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs,
170 BitVector &PhysRegClobbers, SmallSet<int, 32> &StoredFIs,
349 BitVector &PhysRegDefs,
350 BitVector &PhysRegClobbers,
442 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop.
443 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once.
476 BitVector TermRegs(NumRegs);
    [all...]
RegAllocBasic.cpp 73 BitVector UsableRegs;
ShrinkWrap.cpp 49 #include "llvm/ADT/BitVector.h"
138 BitVector SavedRegs;
SplitKit.h 103 BitVector ThroughBlocks;
174 const BitVector &getThroughBlocks() const { return ThroughBlocks; }
  /external/llvm/lib/Target/AArch64/
AArch64LoadStoreOptimizer.cpp 18 #include "llvm/ADT/BitVector.h"
805 static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs,
806 BitVector &UsedRegs,
903 BitVector ModifiedRegs, UsedRegs;
    [all...]
AArch64CollectLOH.cpp 106 #include "llvm/ADT/BitVector.h"
212 /// Map a basic block to a BitVector.
214 typedef MapVector<const MachineBasicBlock *, BitVector> BlockToRegSet;
296 BitVector &BBKillSet = Kill[&MBB];
    [all...]
  /external/llvm/utils/TableGen/
RegisterInfoEmitter.cpp 19 #include "llvm/ADT/BitVector.h"
522 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
525 const BitVector &Bits,
539 BitVector Values;
    [all...]
  /external/llvm/include/llvm/CodeGen/
ScheduleDAG.h 19 #include "llvm/ADT/BitVector.h"
701 BitVector Visited;
710 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
ScheduleDAGInstrs.h 166 BitVector LiveRegs;
MachineFrameInfo.h 31 class BitVector;
614 BitVector getPristineRegs(const MachineFunction &MF) const;
SelectionDAGNodes.h 22 #include "llvm/ADT/BitVector.h"
    [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.cpp 21 #include "llvm/ADT/BitVector.h"
127 BitVector ARMBaseRegisterInfo::
133 BitVector Reserved(getNumRegs());
  /external/srtp/googlepatches/
vidyo-3-srtp-ws.patch 240 + /* initialize bitvector to zero */
348 - /* initialize bitvector to zero */
457 - /* if the length is greater than the bitvector, return an error */
  /art/compiler/
oat_writer.h 37 class BitVector;
  /art/compiler/optimizing/
find_loops_test.cc 123 const BitVector& blocks = info->GetBlocks();
ssa_liveness_analysis.h     [all...]
  /external/compiler-rt/lib/sanitizer_common/
sanitizer_bitvector.h 10 // Specializer BitVector implementation.
  /external/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 214 void reserveIndirectRegisters(BitVector &Reserved,
  /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/lib/
libulib.a 19 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    [all...]
  /art/runtime/verifier/
reg_type.cc 312 const BitVector& types = GetUnresolvedTypes();
799 const BitVector& unresolved,
reg_type_cache.cc 415 const BitVector& unresolved_part = cmp_type->GetUnresolvedTypes();
417 // BitVector in the final RegType will be made non-expandable.
  /external/clang/lib/Analysis/
LiveVariables.cpp 32 llvm::BitVector enqueuedBlocks;
503 llvm::BitVector everAnalyzedBlock(cfg->getNumBlockIDs());
  /external/clang/test/SemaCXX/
typo-correction.cpp 514 PR18685::BitVector Map; // expected-error-re {{no type named 'BitVector' in namespace 'PR18685'{{$}}}}

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