| /system/core/libpixelflinger/arch-arm64/ |
| t32cb16blend.S | 182 cbz w3, 7f
198 cbz w3, 7f
|
| /external/llvm/test/CodeGen/ARM/ |
| arm-shrink-wrapping.ll | 88 ; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
97 ; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
212 ; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
221 ; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
291 ; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
300 ; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
376 ; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
385 ; THUMB-DISABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
442 ; THUMB-ENABLE: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]]
451 ; THUMB-DISABLE-NEXT: cbz r0, [[ELSE_LABEL:LBB[0-9_]+]
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 63 STATISTIC(NumCmpTermRejs, "Number of ccmps rejected (CmpBB is cbz...)");
72 STATISTIC(NumCompBranches, "Number of cbz/cbnz branches converted");
279 // For tbz and cbz instruction, the opcode is next.
576 // If the Head terminator was one of the cbz / tbz branches with built-in
597 // Insert a SUBS Rn, #0 instruction instead of the cbz / cbnz.
614 bool isZBranch = false; // CmpMI is a cbz/cbnz instruction.
660 MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
685 // If the Head terminator was one of the cbz / tbz branches with built-in
701 // If the Cmp terminator was one of the cbz / tbz branches with
|
| /art/runtime/arch/arm64/ |
| quick_entrypoints_arm64.S | 326 cbz x0, 1f // result zero branch over
459 cbz x0, 1f // did we find the target? if not go to exception delivery
688 cbz w17, .LcallFunction // Exit at end of signature. Shorty 0 terminated.
821 cbz w17, .LcallFunction2 // Exit at end of signature. Shorty 0 terminated.
1076 cbz w0, .Lslow_lock
[all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm64.S | [all...] |
| /device/google/contexthub/firmware/src/cpu/cortexm4f/ |
| atomicBitset.c | 101 " cbz %3, 1f \n"
|
| /external/autotest/client/site_tests/hardware_PerfCounterVerification/src/ |
| find_loop_instructions.py | 85 'b', 'bl', 'blx', 'bx', 'bxj', 'cbz', 'cbnz']
|
| /external/vixl/examples/ |
| crc-checksums.cc | 54 __ Cbz(x1, &end);
|
| sum-array.cc | 45 __ Cbz(w1, &end);
|
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/asm/internal/arch/ |
| arm64.go | 44 "CBZ": true,
|
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.out | 35 130 00035 (testdata/arm64.s:130) CBZ R1
|
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/asm/internal/arch/ |
| arm64.go | 44 "CBZ": true,
|
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm64/ |
| anames.go | 42 "CBZ",
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.out | 35 130 00035 (testdata/arm64.s:130) CBZ R1
|
| /external/llvm/test/CodeGen/AArch64/ |
| analyze-branch.ll | 85 ; CHECK: cbz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
106 ; CHECK: cbz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
|
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | 208 cbz r0, 1f @ result zero branch over
369 cbz r0, 1f @ did we find the target? if not go to exception delivery
537 cbz r0, .Lslow_lock
592 cbz r0, .Lslow_unlock
667 cbz r0, .Lthrow_class_cast_exception
766 @ The offset to .Ldo_aput_null is too large to use cbz due to expansion from READ_BARRIER macro.
770 cbz r2, .Ldo_aput_null
799 cbz r0, .Lthrow_array_store_exception
[all...] |
| /external/boringssl/linux-aarch64/crypto/bn/ |
| armv8-mont.S | 52 cbz x21,.L1st_skip
113 cbz x21,.Linner_skip
425 cbz x27,.Lsqr8x_outer_break
547 cbz x14,.Lsqr8x_outer_loop
714 cbz x27,.Lsqr8x8_post_condition
772 cbz x27,.Lsqr8x_tail_break
1047 cbz x10,.Lmul4x4_post_condition
1104 cbz x10,.Lmul4x_proceed
1247 cbz x10,.Loop_mul4x_break
|
| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| strcmp.S | 100 * The only difference between ARM and Thumb modes is the use of CBZ instruction.
107 cbz \reg, \label
354 /* Using r0 and not ip here because cbz requires low register. */
|
| /bionic/libc/arch-arm/krait/bionic/ |
| strcmp.S | 100 * The only difference between ARM and Thumb modes is the use of CBZ instruction.
107 cbz \reg, \label
353 /* Using r0 and not ip here because cbz requires low register. */
|
| /art/compiler/utils/arm/ |
| assembler_thumb2.h | 194 void cbz(Register rn, Label* target) OVERRIDE;
386 // cbz and cbnz instructions may also need to be replaced with a separate 16-bit compare
417 kCompareAndBranchXZero, // cbz/cbnz.
433 // CBZ/CBNZ variants.
434 kCbxz16Bit, // CBZ/CBNZ rX, label; X < 8; 7-bit positive offset.
646 const Register rn_; // Rn for cbnz/cbz, Rt for literal loads.
[all...] |
| /art/runtime/interpreter/mterp/arm64/ |
| footer.S | 84 cbz x0, MterpFallback // If not, fall back to reference interpreter.
95 cbz w0, MterpExceptionReturn // no local catch, back to caller.
|
| /frameworks/native/opengl/libs/EGL/ |
| getProcAddress.cpp | 69 "cbz x16, 1f\n" \
71 "cbz x16, 1f\n" \
|
| /art/compiler/optimizing/ |
| optimizing_cfi_test.cc | 178 // Push the target out of range of CBZ.
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| strcmp.S | 78 cbz syndrome, .Lloop_aligned
|
| strlen.S | 84 cbz has_nul1, .Lnul_in_data2
|
