| /external/llvm/test/CodeGen/Mips/ |
| fmadd1.ll | 219 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
260 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
308 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
356 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 27 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 25 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 25 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64-el.txt | 88 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
228 0x00 0x28 0xb7 0x44 # CHECK: dmtc1 $23, $f5
|
| valid-mips64.txt | 213 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
214 0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 94 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
249 0x00 0x28 0xb7 0x44 # CHECK: dmtc1 $23, $f5
|
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | [all...] |
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | [all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | [all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 311 void Dmtc1(GpuRegister rt, FpuRegister fs); // MIPS64
|
| assembler_mips64_test.cc | 566 TEST_F(AssemblerMIPS64Test, Dmtc1) {
567 DriverStr(RepeatRF(&mips64::Mips64Assembler::Dmtc1, "dmtc1 ${reg1}, ${reg2}"), "Dmtc1");
[all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 349 { kFpMask | (0x1f << 21), kCop1 | (0x05 << 21), "dmtc1", "Td" },
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 70 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| valid-mips3.txt | 143 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 74 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3-el.txt | 91 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 91 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 77 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 81 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 81 dmtc1 $s0,$f14
|
| /art/compiler/optimizing/ |
| code_generator_mips64.cc | 702 __ Dmtc1(gpr, destination.AsFpuRegister<FpuRegister>());
711 __ Dmtc1(source.AsRegister<GpuRegister>(), destination.AsFpuRegister<FpuRegister>());
[all...] |
