| /external/llvm/test/CodeGen/ARM/ |
| vceq.ll | 38 %tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
78 %tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
|
| vcge.ll | 68 %tmp3 = fcmp oge <2 x float> %tmp1, %tmp2
138 %tmp3 = fcmp oge <4 x float> %tmp1, %tmp2
193 %0 = fcmp ole <4 x float> undef, zeroinitializer
|
| vcgt.ll | 69 %tmp3 = fcmp ogt <2 x float> %tmp1, %tmp2
139 %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
170 %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2
|
| /external/llvm/test/CodeGen/X86/ |
| avx512-mov.ll | 365 %mask = fcmp one <16 x float> %mask1, zeroinitializer
376 %mask = fcmp one <16 x float> %mask1, zeroinitializer
387 %mask = fcmp one <16 x float> %mask1, zeroinitializer
398 %mask = fcmp one <16 x float> %mask1, zeroinitializer
409 %mask = fcmp one <8 x double> %mask1, zeroinitializer
420 %mask = fcmp one <8 x double> %mask1, zeroinitializer
431 %mask = fcmp one <8 x double> %mask1, zeroinitializer
442 %mask = fcmp one <8 x double> %mask1, zeroinitializer
|
| avx512-select.ll | 28 %cmp = fcmp oge float %a, %eps
38 %cmp = fcmp oge double %a, %eps
|
| fast-isel-select-pseudo-cmov.ll | 13 %1 = fcmp one float %a, %b
24 %1 = fcmp one double %a, %b
|
| machine-cp.ll | 90 %v16 = fcmp olt <16 x float> %x, zeroinitializer
97 %v69 = fcmp ogt <16 x float> %v22, zeroinitializer
|
| pseudo_cmov_lower2.ll | 13 %c1 = fcmp oge float %p1, 0.000000e+00
34 %c1 = fcmp oge float %p1, 0.000000e+00
|
| fast-isel-deadcode.ll | 50 %cmp = fcmp oeq x86_fp80 %0, %1
95 %cmp.i = fcmp oeq float %1, 1.000000e+00
118 %cmp3.i = fcmp olt float %1, 0x3E45798EE0000000
|
| /external/llvm/test/DebugInfo/ARM/ |
| s-super-register.ll | 17 %cmp7 = fcmp olt float %call, %call16, !dbg !12
25 %cmp = fcmp olt float %inc, %call1, !dbg !12
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| hoist-loads.ll | 20 %cmp3 = fcmp oeq float %0, 0.000000e+00
52 %cmp3 = fcmp oeq float %0, 0.000000e+00
|
| /external/llvm/test/MC/AArch64/ |
| arm64-fp-encoding.s | 188 fcmp h1, h2
189 fcmp s1, s2
190 fcmp d1, d2
191 fcmp h1, #0.0
192 fcmp s1, #0.0
193 fcmp d1, #0.0
201 ; FP16: fcmp h1, h2 ; encoding: [0x20,0x20,0xe2,0x1e]
203 ; NO-FP16-NEXT: fcmp h1, h2
204 ; CHECK: fcmp s1, s2 ; encoding: [0x20,0x20,0x22,0x1e]
205 ; CHECK: fcmp d1, d2 ; encoding: [0x20,0x20,0x62,0x1e
[all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/llvm/test/Transforms/Float2Int/ |
| basic.ll | 50 %3 = fcmp ult float %1, %2
193 ; CHECK: %3 = fcmp false float %1, %2
199 %3 = fcmp false float %1, %2
244 ; CHECK: fcmp
249 %3 = fcmp olt double %2, 0.000000e+00
|
| /external/llvm/unittests/IR/ |
| IRBuilderTest.cpp | 134 Instruction *FDiv, *FAdd, *FCmp, *FCall;
195 FCmp = cast<Instruction>(FC);
196 EXPECT_FALSE(FCmp->hasAllowReciprocal());
206 FCmp = cast<Instruction>(FC);
207 EXPECT_TRUE(FCmp->hasAllowReciprocal());
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ia64-ic.tbl | 8 fcmp-s0; fcmp[Field(sf)==s0]
9 fcmp-s1; fcmp[Field(sf)==s1]
10 fcmp-s2; fcmp[Field(sf)==s2]
11 fcmp-s3; fcmp[Field(sf)==s3]
222 pr-gen-writers-fp; fclass, fcmp
228 pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, clz, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, hint.f, hint.i, hint.m, hint.x, IC:invala-all, itc.i, itc.d (…)
[all...] |
| microblaze-opc.h | 262 {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
263 {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
264 {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
265 {"fcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000240, OPCODE_MASK_H4, fcmp_gt, arithmetic_inst },
266 {"fcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000250, OPCODE_MASK_H4, fcmp_ne, arithmetic_inst },
267 {"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
268 {"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Float2Int.cpp | 39 // float to the int domain: fptoui, fptosi and fcmp. Walk up the def-use
92 // Given a FCmp predicate, return a matching ICmp predicate if one
142 case Instruction::FCmp:
228 case Instruction::FCmp:
296 case Instruction::FCmp:
298 assert(Ops.size() == 2 && "FCmp is a binary operator!");
481 case Instruction::FCmp: {
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64-f128.ll | 480 %cmp = fcmp olt fp128 %a, %b
490 %cmp = fcmp ole fp128 %a, %b
500 %cmp = fcmp ogt fp128 %a, %b
510 %cmp = fcmp oge fp128 %a, %b
520 %cmp = fcmp oeq fp128 %a, %b
530 %cmp = fcmp une fp128 %a, %b
669 %cmp = fcmp ogt fp128 %a, %b
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter6/ |
| codegen.ml | 39 let i = build_fcmp Fcmp.Ult lhs_val rhs_val "cmptmp" builder in
71 let cond_val = build_fcmp Fcmp.One cond zero "ifcond" builder in
165 let end_cond = build_fcmp Fcmp.One end_cond zero "loopcond" builder in
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fp128.ll | 133 %val = fcmp ole fp128 %lhs, %rhs
150 %val = fcmp ugt fp128 %lhs, %rhs
168 %cond = fcmp olt fp128 %lhs, %rhs
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| schedule-vs-if-nested-loop.ll | 10 %4 = fcmp ult float %0, 0.000000e+00
102 %79 = fcmp uge float %temp4.0, %0
112 %86 = fcmp une float %2, %temp4.0
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select.ll | 344 %s = fcmp olt float %x, %y
376 %s = fcmp ole float %x, %y
408 %s = fcmp ogt float %x, %y
440 %s = fcmp oge float %x, %y
472 %s = fcmp oeq float %x, %y
511 %s = fcmp one float %x, %y
543 %s = fcmp olt double %x, %y
575 %s = fcmp ole double %x, %y
607 %s = fcmp ogt double %x, %y
639 %s = fcmp oge double %x, %
[all...] |
| /external/llvm/test/CodeGen/Mips/msa/ |
| llvm-stress-s1704963983.ll | 84 %Cmp46 = fcmp ugt float 0xB856238A00000000, 0x47DA795E40000000
96 %Cmp54 = fcmp ole float 0x47DA795E40000000, 0xB856238A00000000
116 %Cmp69 = fcmp ord double 0.000000e+00, 0.000000e+00
|
| llvm-stress-s1935737938.ll | 41 %Cmp17 = fcmp one float 0xBD946F9840000000, %B15
80 %Cmp45 = fcmp une float 0x3AFCE1A0C0000000, 0.000000e+00
128 %Cmp73 = fcmp ugt double 0x235104F0E94F406E, 0x235104F0E94F406E
|
