| /external/llvm/test/CodeGen/PowerPC/ |
| optcmp.ll | 116 %cmp = fcmp ogt double %a, %b
129 %cmp = fcmp ogt float %a, %b
|
| /art/test/570-checker-select/src/ |
| Main.java | 348 /// CHECK-NEXT: fcmp
362 /// CHECK-NEXT: fcmp
376 /// CHECK-NEXT: fcmp
390 /// CHECK-NEXT: fcmp
407 /// CHECK-NEXT: fcmp
424 /// CHECK-NEXT: fcmp
|
| /external/llvm/lib/Analysis/ |
| BranchProbabilityInfo.cpp | 478 FCmpInst *FCmp = dyn_cast<FCmpInst>(Cond);
479 if (!FCmp)
483 if (FCmp->isEquality()) {
486 isProb = !FCmp->isTrueWhenEqual();
487 } else if (FCmp->getPredicate() == FCmpInst::FCMP_ORD) {
490 } else if (FCmp->getPredicate() == FCmpInst::FCMP_UNO) {
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-scalar-fp.txt | 163 # FP16: fcmp h1, h2
164 # CHECK: fcmp s1, s2
165 # CHECK: fcmp d1, d2
166 # FP16: fcmp h1, #0.0
167 # CHECK: fcmp s1, #0.0
168 # CHECK: fcmp d1, #0.0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| am33-2.c | 487 def_am_insn (fcmp, fsfs, 3, 0xf954,
489 def_am_insn (fcmp, i32fs, 7, 0xfe35,
526 am_insn (fcmp, fsfs),
527 am_insn (fcmp, i32fs),
579 def_am_insn (fcmp, fdfd, 3, 0xf9d4,
608 am_insn (fcmp, fdfd),
|
| am33-2.d | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/ |
| sh2a-or-sh3e.s | 180 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
181 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
|
| sh2e.s | 25 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
26 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
|
| sh3e.s | 192 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
193 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/ |
| sh2a-or-sh3e.s | 180 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
181 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
|
| sh2e.s | 25 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
26 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
|
| sh3e.s | 192 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
193 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| si-sgpr-spill.ll | 203 %186 = fcmp uge float 1.000000e+00, %185
207 %190 = fcmp uge float 3.000000e+00, %189
249 %225 = fcmp oge float %temp24.0, %191
276 %246 = fcmp oge float %temp30.0, %245
297 %259 = fcmp oge float %temp24.1, %195
566 %525 = fcmp uge float %524, 0.000000e+00
579 %538 = fcmp uge float %537, 0.000000e+00
639 %594 = fcmp oge float %temp30.1, %593
[all...] |
| schedule-vs-if-nested-loop-failure.ll | 14 %2 = fcmp ult float %0, 0.000000e+00
120 %85 = fcmp uge float %temp4.0, %0
131 %93 = fcmp une float %1, %temp4.0
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ia64-raw.tbl | 13 AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF
14 AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF
15 AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF
16 AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF
17 AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF
18 AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF
19 AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF
20 AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF
21 AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
22 AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; implied
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 40 /// Similar to getICmpCode but for FCmpInst. This encodes a fcmp predicate into
63 llvm_unreachable("Unexpected FCmp predicate!");
80 /// operands into either a FCmp instruction. isordered is passed in to determine
81 /// which kind of predicate to use in the new fcmp instruction.
87 default: llvm_unreachable("Illegal FCmp code!");
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| select.ll | 232 %cmp = fcmp oeq float %f2, %f3
269 %cmp = fcmp olt float %f2, %f3
306 %cmp = fcmp ogt float %f2, %f3
343 %cmp = fcmp ogt float %f2, %f3
380 %cmp = fcmp oeq double %f2, %f3
417 %cmp = fcmp olt double %f2, %f3
454 %cmp = fcmp ogt double %f2, %f3
494 %cmp = fcmp ogt double %f2, %f3
539 %cmp = fcmp oeq float %f2, %f3
583 %cmp = fcmp olt float %f2, %f
[all...] |
| /external/clang/test/OpenMP/ |
| parallel_reduction_codegen.cpp | 258 // CHECK: [[VAR1_BOOL:%.+]] = fcmp une float [[TO_FLOAT]], 0.0
262 // CHECK: [[VAR1_REDUCTION_BOOL:%.+]] = fcmp une float [[TO_FLOAT]], 0.0
275 // CHECK: [[CMP:%.+]] = fcmp olt float [[T_VAR1_VAL]], [[T_VAR1_PRIV_VAL]]
314 // CHECK: [[VAR1_BOOL:%.+]] = fcmp une float [[TO_FLOAT]], 0.0
318 // CHECK: [[VAR1_REDUCTION_BOOL:%.+]] = fcmp une float [[TO_FLOAT]], 0.0
336 // CHECK: [[CMP:%.+]] = fcmp olt float
412 // CHECK: [[VAR1_BOOL:%.+]] = fcmp une float [[TO_FLOAT]], 0.0
416 // CHECK: [[VAR1_REDUCTION_BOOL:%.+]] = fcmp une float [[TO_FLOAT]], 0.0
429 // CHECK: [[CMP:%.+]] = fcmp olt float [[T_VAR1_LHS_VAL]], [[T_VAR1_RHS_VAL]]
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| fast-math.ll | 165 %cmp = fcmp ogt float %x, %y
747 ; CHECK-NEXT: fcmp fast ogt float %a, %b
757 ; CHECK-NEXT: fcmp nnan nsz ogt float %a, %b
768 ; CHECK-NEXT: fcmp fast ogt double %a, %b
778 ; CHECK-NEXT: fcmp nnan nsz ogt fp128 %a, %b
792 ; CHECK-NEXT: fcmp nnan nsz olt float %a, %b
802 ; CHECK-NEXT: fcmp fast olt float %a, %b
812 ; CHECK-NEXT: fcmp nnan nsz olt double %a, %b
822 ; CHECK-NEXT: fcmp fast olt fp128 %a, %b
|
| load-cmp.ll | 77 %R = fcmp oeq double %Q, 1.0
125 %R = fcmp ogt double %Q, 0.0
136 %R = fcmp olt double %Q, 0.0
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-ccmp.ll | 147 %cmp1 = fcmp oge float %div, 1.700000e+01
323 ; CHECK: fcmp d0, d2
329 %1 = fcmp one double %v1, %v2
330 %2 = fcmp oeq double %v2, 13.0
331 %3 = fcmp oeq double %v1, 42.0
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| codegen.ml | 68 let i = build_fcmp Fcmp.Ult lhs_val rhs_val "cmptmp" builder in
101 let cond_val = build_fcmp Fcmp.One cond zero "ifcond" builder in
222 let end_cond = build_fcmp Fcmp.One end_cond zero "loopcond" builder in
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXGenericToNVVM.cpp | 317 case Instruction::FCmp:
318 // CompareConstantExpr (fcmp)
320 "on float point CompareConstantExpr (fcmp)!");
|
| /external/llvm/test/CodeGen/ARM/ |
| thumb2-size-reduction-internal-flags.ll | 63 %cmp20 = fcmp olt double %div19, %prob
99 %cmp59 = fcmp olt double %div58, %prob
144 %cmp93 = fcmp olt double %div92, %prob
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| reduction.ll | 342 %cmp3 = fcmp ogt float %0, %1
346 %cmp6 = fcmp ogt float %1, 1.000000e+00
354 %cmp14 = fcmp ogt float %0, 2.000000e+00
387 %cmp3 = fcmp ogt float %0, %1
391 %cmp6 = fcmp ogt float %1, 1.000000e+00
399 %cmp14 = fcmp ogt float %0, 2.000000e+00
|
