| /external/llvm/test/CodeGen/Mips/msa/ |
| llvm-stress-s2090927243-simplified.ll | 2 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s
|
| special.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
5 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
|
| vecs10.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| 2r_vector_scalar.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
8 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
10 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \
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| 2rf_fq.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| 3rf_exdo.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| endian.ll | 1 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s
2 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
|
| i10.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| i5-a.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| i5-s.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| inline-asm.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
|
| 2rf_exup.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| 2rf_float_int.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| 3r-v.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| 3r_splat.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
6 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \
|
| 3rf_4rf.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
| /external/llvm/test/MC/Mips/ |
| nooddspreg-cmdarg.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg -filetype=obj -o - | \
|
| nooddspreg.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \
|
| oddspreg.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \
24 # RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \
|
| /external/llvm/test/CodeGen/Mips/ |
| abiflags32.ll | 2 ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr=fp64 %s -o - | FileCheck -check-prefix=CHECK-64 %s
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUSubtarget.cpp | 39 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
47 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
69 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
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| AMDGPUSubtarget.h | 67 bool FP64;
139 return FP64;
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.td | 32 def FP64 : WebAssemblyReg<"%FP64">;
56 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
|
| WebAssemblyRegisterInfo.cpp | 49 WebAssembly::FP64})
93 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 111 MachineBasicBlock::iterator I, bool FP64) const;
113 MachineBasicBlock::iterator I, bool FP64) const;
|
