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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/
sh4a.s     [all...]
sh2a.s 245 fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e (…)
    [all...]
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/
sh2a-or-sh4.s 39 fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
230 fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
sh4.s     [all...]
sh4a.s     [all...]
sh2a.s 245 fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e (…)
    [all...]
  /external/llvm/test/MC/Disassembler/PowerPC/
ppc64-encoding-fp.txt 138 # CHECK: fsqrt 2, 3
141 # CHECK: fsqrt. 2, 3
  /external/llvm/test/MC/Mips/mips32r2/
invalid-msa.s 37 fsqrt.d $w3,$w1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
38 fsqrt.w $w5,$w15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/
list-insns.s 42 FSQRT $132,ROUND_UP,$14
43 FSQRT $11,$141
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyInstrFloat.td 23 defm SQRT : UnaryFP<fsqrt, "sqrt">;
  /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/x86/
anames.go 331 "FSQRT",
  /prebuilts/go/darwin-x86/src/cmd/internal/obj/x86/
anames.go 328 "FSQRT",
  /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/x86/
anames.go 331 "FSQRT",
  /prebuilts/go/linux-x86/src/cmd/internal/obj/x86/
anames.go 328 "FSQRT",
  /toolchain/binutils/binutils-2.25/opcodes/
microblaze-opcm.h 43 fint, fsqrt, enumerator in enum:microblaze_instr
m88k-dis.c 207 {0x84007800,"fsqrt.ss ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} },
208 {0x84007820,"fsqrt.sd ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} },
209 {0x84007880,"fsqrt.ds ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {5,1,PFLT,FLT ,0,0,1,1,0,0,0,1,0,0,0,0} },
210 {0x840078a0,"fsqrt.dd ",{21,5,REG} ,{0,5,REG} ,NO_OPERAND , {6,1,PFLT,FLT ,0,0,1,1,0,0,0,1,1,0,0,0} },
    [all...]
sh64-opc.c 273 /* 001110gggggg0101ggggggffffff0000 fsqrt.d <A_DREG_G>,<A_DREG_F> */
274 { "fsqrt.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38050000
276 /* 001110gggggg0100ggggggffffff0000 fsqrt.s <A_FREG_G>,<A_FREG_F> */
277 { "fsqrt.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38040000
    [all...]
  /external/llvm/test/MC/AArch64/
arm64-fp-encoding.s 146 fsqrt h1, h2
147 fsqrt s1, s2
148 fsqrt d1, d2
150 ; FP16: fsqrt h1, h2 ; encoding: [0x41,0xc0,0xe1,0x1e]
152 ; NO-FP16-NEXT: fsqrt h1, h2
153 ; CHECK: fsqrt s1, s2 ; encoding: [0x41,0xc0,0x21,0x1e]
154 ; CHECK: fsqrt d1, d2 ; encoding: [0x41,0xc0,0x61,0x1e]
fullfp16-neon-neg.s 28 fsqrt.4h v0, v0
52 fsqrt.8h v0, v0
378 fsqrt v4.4h, v0.4h
380 fsqrt v6.8h, v8.8h
  /external/valgrind/none/tests/ppc32/
round.c 33 FMSUB, FNMADD, FNMSUB, FSQRT
44 "fnmsub", "fsqrt"
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2)
1034 case FSQRT:
1139 case FSQRT:
1140 UNOP("fsqrt");
1208 for (op = FADD; op <= FSQRT; op++) {
  /external/llvm/lib/Target/SystemZ/
SystemZInstrFP.td 296 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
297 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
298 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
300 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
301 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/
476.s 187 fsqrt 10,11
188 fsqrt. 10,11
a2.s 232 fsqrt. 20,21
233 fsqrt 20,21
  /external/valgrind/VEX/useful/
x87_to_vex_and_back.c 160 asm volatile ("fldln2 ; fldlg2 ; fchs ; fsqrt");
  /ndk/sources/host-tools/nawk-20071023/
awk.h 116 #define FSQRT 2

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