| /external/llvm/test/CodeGen/AMDGPU/ |
| cvt_flr_i32_f32.ll | 52 %x.fneg = fsub float -0.000000e+00, %x
66 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
|
| ffloor.f64.ll | 38 %neg = fsub double 0.0, %x
55 %neg = fsub double 0.0, %abs
|
| llvm.AMDGPU.fract.f64.ll | 37 %neg = fsub double 0.0, %val
56 %neg = fsub double 0.0, %abs
|
| llvm.AMDGPU.fract.ll | 46 %neg = fsub float 0.0, %val
61 %neg = fsub float 0.0, %abs
|
| commute_modifiers.ll | 30 %x.fneg.fabs = fsub float -0.000000e+00, %x.fabs
44 %x.fneg = fsub float -0.000000e+00, %x
94 %y.fneg = fsub float -0.000000e+00, %y
112 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
150 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
|
| big_alu.ll | 125 %113 = fsub float -0.000000e+00, %92
126 %114 = fsub float -0.000000e+00, %93
127 %115 = fsub float -0.000000e+00, %94
231 %213 = fsub float -0.000000e+00, %212
236 %218 = fsub float -0.000000e+00, %217
241 %223 = fsub float -0.000000e+00, %222
287 %269 = fsub float -0.000000e+00, %268
292 %274 = fsub float -0.000000e+00, %273
297 %279 = fsub float -0.000000e+00, %278
352 %334 = fsub float -0.000000e+00, %33
[all...] |
| sgpr-copy.ll | 22 %27 = fsub float -0.000000e+00, %22
83 %67 = fsub float -0.000000e+00, %26
97 %78 = fsub float -0.000000e+00, %70
99 %80 = fsub float -0.000000e+00, %79
117 %91 = fsub float -0.000000e+00, %71
119 %93 = fsub float -0.000000e+00, %92
138 %108 = fsub float -0.000000e+00, %102
140 %110 = fsub float -0.000000e+00, %104
142 %112 = fsub float -0.000000e+00, %106
|
| /external/llvm/test/CodeGen/ARM/ |
| fnegs.ll | 25 %1 = fsub float -0.000000e+00, %0 ; <float> [#uses=2]
89 %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast
|
| vneg.ll | 31 %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
63 %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
|
| /external/llvm/test/CodeGen/PowerPC/ |
| vsx-elementary-arith.ll | 24 %sub = fsub float %0, %1
81 %sub = fsub double %0, %1
|
| /external/llvm/test/CodeGen/X86/ |
| 2009-08-14-Win64MemoryIndirectArg.ll | 35 %texDiffDX = fsub <4 x float> %texCoordDX, %texCoord ; <<4 x float>> [#uses=1]
36 %texDiffDY = fsub <4 x float> %texCoordDY, %texCoord ; <<4 x float>> [#uses=1]
|
| fold-load-binops.ll | 55 %r = fsub float %a, %b
72 %r = fsub double %a, %b
|
| pr20020.ll | 47 %sub = fsub double %2, %3
50 %sub8 = fsub double %4, %5
|
| pseudo_cmov_lower2.ll | 19 %d5 = fsub double %d2, %d3
40 %d5 = fsub double %d2, %d3
|
| /external/llvm/test/Transforms/LoopVectorize/X86/ |
| unroll_selection.ll | 27 %11 = fsub double %10, %5
34 %18 = fsub double %4, %5
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| crash_lencod.ll | 50 %sub91 = fsub double %mul89, %mul90
54 %sub96 = fsub double %mul94, %mul95
|
| external_user.ll | 75 %sub = fsub float 0.000000e+00, %1
79 %sub3 = fsub float 1.000000e+00, %1
|
| /external/valgrind/none/tests/ppc32/ |
| round.stdout.exp | [all...] |
| /external/valgrind/none/tests/ppc64/ |
| round.stdout.exp | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| i386.h | 27 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
28 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
|
| /external/llvm/test/Transforms/Reassociate/ |
| fast-ReassociateVector.ll | 52 ; CHECK-NEXT: %R = fsub <2 x float> %X, %Y
57 %R = fsub <2 x float> %X, %Y
114 %3 = fsub fast <2 x double> <double 0.000000e+00, double 0.000000e+00>, %a
127 %c = fsub fast <2 x float> <float 0.000000e+00, float 0.000000e+00>, %d
129 %f = fsub fast <2 x float> <float 0.000000e+00, float 0.000000e+00>, %e
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mn10300/ |
| am33-2.d | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 191 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
461 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
463 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
467 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
473 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
479 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
485 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
492 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
500 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
[all...] |
| /external/clang/test/CodeGen/ |
| builtins-ppc-vsx.c | 514 // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
516 // CHECK-LE: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
520 // CHECK: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{[0-9]+}}
522 // CHECK-LE: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %{{[0-9]+}}
551 // CHECK-NEXT: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[FM]]
553 // CHECK-LE-NEXT: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %[[FM]]
557 // CHECK-NEXT: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %[[FM]]
559 // CHECK-LE-NEXT: fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %[[FM]]
562 // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{[0-9]+}}
564 // CHECK: fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, (…)
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| aarch64-a57-fp-load-balancing.ll | 46 %sub = fsub fast double %add6, %mul7
107 %sub = fsub fast double %add10, %mul13
144 %sub = fsub fast double %add6, %mul7
202 %sub = fsub fast float %add10, %mul13
239 %sub = fsub fast float %add6, %mul7
281 %sub = fsub fast double %add6, %mul7
316 %sub = fsub fast double %add6, %mul7
|
