| /toolchain/binutils/binutils-2.25/gas/doc/ |
| c-i386.texi | 20 The i386 version @code{@value{AS}} supports both the original Intel 386
22 extending the Intel architecture to 64-bits.
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
65 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
273 @itemx -mmnemonic=@var{intel}
281 @itemx -msyntax=@var{intel}
358 * i386-Variations:: AT&T Syntax versus Intel Syntax
363 @subsection AT&T Syntax versus Intel Syntax
378 @code{@value{AS}} now supports assembly using Intel assembler syntax.
379 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switche
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| /frameworks/base/docs/html/ndk/guides/ |
| abis.jd | 215 -march=i686 -mtune=intel -mssse3 -mfpmath=sse -m32
224 The generated code is an optimization balanced across the top Intel 32-bit
227 refer to <a href="http://software.intel.com/blogs/2012/09/26/gcc-x86-performance-hints">GCC
252 GCC online documentation: Intel 386 and AMD x86-64 Options</a></li>
256 href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf"
257 >Intel IA-32 Intel Architecture Software Developer's Manual, Volume 2:
260 href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf">Intel
261 IA-32 Intel Architecture Software Developer's Manual, Volume 3: Syste
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| /toolchain/binutils/binutils-2.25/opcodes/ |
| i386-opc.h | 1 /* Declarations for Intel 80386 opcode table
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required *
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| ChangeLog-2010 | 9 2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
77 2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
87 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
92 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
98 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
155 2010-10-02 H.J. Lu <hongjiu.lu@intel.com>
311 2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
318 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
326 2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
350 2010-08-05 H.J. Lu <hongjiu.lu@intel.com
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_fragprog.c | 1316 struct intel_context *intel = intel_context(ctx); local
1340 struct intel_context *intel = intel_context(ctx); local
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| /external/valgrind/coregrind/m_initimg/ |
| initimg-solaris.c | 690 | VKI_AV_386_SSSE3; /* Intel SSSE3 insns */
704 AV_386_SSE4_1 Intel SSE4.1 insns
705 AV_386_SSE4_2 Intel SSE4.2 insns
706 AV_386_MOVBE Intel MOVBE insns
707 AV_386_AES Intel AES insns
708 AV_386_PCLMULQDQ Intel PCLMULQDQ insn
709 AV_386_XSAVE Intel XSAVE/XRSTOR insns
710 AV_386_AVX Intel AVX insns
712 AV_386_VMX Intel VMX support
738 | VKI_AV_386_SSSE3; /* Intel SSSE3 insns *
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| /toolchain/binutils/binutils-2.25/gas/testsuite/ |
| ChangeLog-2010 | 29 2010-12-30 H.J. Lu <hongjiu.lu@intel.com>
72 * gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
74 * gas/i386/ilp32/x86-64-aes-intel.d: Likewise.
79 * gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
81 * gas/i386/ilp32/x86-64-avx-swap-intel.d: Likewise.
84 * gas/i386/ilp32/x86-64-cbw-intel.d: Likewise.
86 * gas/i386/ilp32/x86-64-clmul-intel.d: Likewise.
88 * gas/i386/ilp32/x86-64-crc32-intel.d: Likewise.
93 * gas/i386/ilp32/x86-64-disp-intel.d: Likewise.
97 * gas/i386/ilp32/x86-64-ept-intel.d: Likewise
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| /bionic/libm/include/amd64/machine/ |
| fpu.h | 38 * The i387 defaults to Intel extended precision mode and round to nearest,
|
| /development/ndk/platforms/android-21/arch-x86_64/include/machine/ |
| fpu.h | 38 * The i387 defaults to Intel extended precision mode and round to nearest,
|
| /device/asus/fugu/ |
| BoardConfig.mk | 18 -include vendor/intel/fugu/BoardConfigVendor.mk
133 persist.intel.isv.vpp = 1 \
134 persist.intel.isv.frc = 1
157 -include device/intel/common/external/external.mk
|
| /device/asus/fugu/self-extractors/root/ |
| device-vendor.mk | 25 $(call inherit-product-if-exists, vendor/intel/$(LOCAL_STEM))
|
| /device/intel/edison/flash_tools/ |
| brillo-flashall-edison.sh | 35 "${ANDROID_BUILD_TOP}/vendor/bsp/intel/edison/uboot_firmware")
|
| /external/apache-harmony/security/src/test/api/java/org/apache/harmony/security/tests/java/security/serialization/ |
| CodeSignerTest.java | 40 * @see com.intel.drl.test.SerializationTest#getData()
|
| TimestampTest.java | 39 * @see com.intel.drl.test.SerializationTest#getData()
|
| /external/autotest/client/bin/ |
| kvm_control.py | 26 raise error.TestError("CPU Must be AMD or Intel, and must be KVM ready.")
|
| /external/autotest/client/tests/kvmtest/ |
| README | 5 * Host needs to have Intel/AMD Virtualization hardware support.
|
| /external/chromium-trace/catapult/telemetry/telemetry/internal/browser/ |
| user_agent.py | 7 'Mozilla/5.0 (Macintosh; Intel Mac OS X 10_7_3) '
|
| /external/clang/test/CodeGen/ |
| ms-inline-asm-align.c | 6 // Intel inline assembly parser should rewrite to the appropriate form depending
|
| /external/clang/test/CodeGenCXX/ |
| mangle-ms-vector-types.cpp | 28 // We have a custom mangling for vector types not standardized by Intel.
|
| /external/fio/examples/ |
| enospc-pressure.fio | 42 verify=crc32c-intel
|
| /external/google-breakpad/src/testing/gtest/xcode/Config/ |
| General.xcconfig | 10 // Build for PPC and Intel, 32- and 64-bit
|
| /external/google-breakpad/src/third_party/libdisasm/ |
| TODO | 3 intel: jmpf -> jmp, callf -> call
|
| /external/kernel-headers/original/uapi/linux/ |
| fdreg.h | 92 * http://www.intel.com/design/archives/periphrl/docs/29046803.htm */
114 #define FDC_8272A 0x20 /* Intel 8272a, NEC 765 */
115 #define FDC_765ED 0x30 /* Non-Intel 1MB-compatible FDC, can't detect */
116 #define FDC_82072 0x40 /* Intel 82072; 8272a + FIFO + DUMPREGS */
|
| nvme_ioctl.h | 3 * Copyright (c) 2011-2014, Intel Corporation.
|
| stm.h | 3 * Copyright (c) 2014, Intel Corporation.
|
